Digital Electronics Lab-3

Et
Digital Electronics
Lab Manual
for
[D.E.C.E 2nd Year - III Semester ]
N.DHANANJAYA
Author
*
H.O.D of Electronics
*
Director
*
Senior Lecturer
*
Publisher
Price Rs: 180
Maanya’s M.G.B Publications

Hyderabad : 9290429549
Tirupati. Cell: 9000 3050 79

DE Lab Manual
First Edition: June – 2019
© All Rights Reserved
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Name of the College: …………………………………………
Department of ………………………………………………
Certificate
Certified that this is the bonafide record of practical work done in the
Laboratory by MS/Mr…………………………………………………………….
a student of………………………………………………………………………..
with PIN No:………………...………….….during the year……….…………...
No. of Practicals Conducted
No. of Practicals Attended
Marks Awarded
Signature - LECTURER Signature - HEAD OF THE DEPARTMENT
Submitted for the Practical Examination held on: .………………………….……………………………….……
1. EXAMINER 2. EXAMINER
Pointer
Sl.No. Date Name of the Experiment Page No.
1
Introduction to the Breadboard
Introduction
The breadboard consists of “two terminal strips” and “two bus strips” (often
broken in the centre). Each bus strip has two rows of contacts. Each of the two rows
of contacts are a node. That is, each contact along a row on a bus strip is connected
together (inside the breadboard). Bus strips are used primarily for power supply
connections, but are also used for any node requiring a large number of connections.
Each terminal strip has 60 rows and 5 columns of contacts on each side of the centre
gap. Each row of 5 contacts is a node.
Fig. 0.1
M.G.B Publications Digital Electronics Lab Practice

2
You will build your circuits on the terminal strips by inserting the leads of
circuit components into the contact receptacles and making connections with 22-26
gauge wire. There are wire cutter/strippers and a spool of wire in the lab. It is a
good practice to wire +5V and 0V power supply connections to separate bus strips.
The 5V supply MUST NOT BE EXCEEDED since this will damage the ICs
(Integrated circuits) used during the experiments. Incorrect connection of power to
the ICs could result in them exploding or becoming very hot - with the possible
serious injury occurring to the people working on the experiment! Ensure that the
power supply polarity and all components and connections are correct before
switching on power .
Steps for wiring a circuit
Throughout these experiments we will use TTL chips to build circuits. The
steps for wiring a circuit should be completed in the order described below:
1. Turn the power OFF (Trainer Kit) before you build anything.
2. Make sure the power is off before you build anything.
3. Connect the +5V and ground (GND) leads of the power supply to the
power and ground bus strips on your breadboard.
4. Plug the chips you will be using into the breadboard. Point all the chips in
the same direction with pin 1 at the upper-left corner. (Pin 1 is often
identified by a dot or a notch next to it on the chip package).
5. Connect +5V and GND pins of each chip to the power and ground bus
strips on the breadboard.
6. Select a connection on your schematic and place a piece of hook-up wire

between corresponding pins of the chips on your breadboard. It is better to
make the short connections before the longer ones. Mark each connection
on your schematic as you go, so as not to try to make the same connection
again at a later stage.
7. Get one of your group members to check the connections, before you turn
the power on.
8. If an error is made turn the power off immediately before you begin to
rewire the circuit.

3
9. At the end of the laboratory session, collect you hook-up wires, chips and
all equipment and return them to the demonstrator.
10. Tidy (arranged neatly and in order) the area that you were working in and
leave it in the same condition as it was before you started.
Common Causes of Problems
1. Not connecting the ground and/or power pins for all chips.
2. Not turning on the power supply before checking the operation of the
circuit.
3. Leaving out wires.
4. Plugging wires into the wrong holes.
5. Driving a single gate input with the outputs of two or more gates
6. Modifying the circuit with the power on.
Example: Implementation of a Logic Circuit
Build a circuit to implement the Boolean function Y = A ⋅ B .
Hex Inverter: IC 7404 Quad 2 Input NAND: IC 7400

Fig. 0.2

4
Fig. 0.3 The complete designed and connected circuit

Sometimes the chip manufacturer may denote the first pin by a small
indented circle above the first pin of the chip. Place your chips in the same direction,
to save confusion at a later stage. Remember that you must connect power to the
chips to get them to work.
………………………………………………………………………………………………….
If you locate any errors in this manual, please e-mail:
mgbdhananjaya@gmail.com
………………………………………………………………………………………………….

5
Identification of Digital ICs
Date: ................................
Aim
1. To identify the given digital ICs.

2. To draw the pin diagrams of TTL and CMOS ICs of AND, OR, NOT, NAND,
NOR and XOR gates with two and three inputs.
Theory
TTL 74XX Series ICs

Quad 2-input TTL Gates
IC No Description
7400 Quad 2-input NAND gate
7402 Quad 2-input NOR gate
7404 Hex inverter
7408 Quad 2-input AND gate
7432 Quad 2-input OR gate
7486 Quad 2-input EXOR gate
Triple 3-input TTL gates

IC No Description
7410 Triple 3-input NAND gate
7411 Triple 3-input AND gate
7427 Triple 3-input NOR gate

6
CMOS 40XX Series ICs

Quad 2-input CMOS gates
IC No Description
4001 Quad 2-input NOR
4011 Quad 2-input NAND
4069 Hex inverter
4070 Quad 2-input EX-OR
4071 Quad 2-input OR
4081 Quad 2-input AND
Triple 3-input CMOS gates

IC No Description
4023 Triple 3-input NAND
4025 Triple 3-input NOR
4073 Triple 3-input AND
4075 Triple 3-input OR

7
Pin Diagrams
7400 Quad 2-input NAND gate
(a) Pin Diagram (b) Logic Symbol
7402 Quad 2-input NOR gate

8
7404 Hex inverter
7408 Quad 2-input AND gate

9
7432 Quad 2-input OR gate
7486 Quad 2-input EXOR gate

10
7410 triple 3-input NAND gate
(a) Pin Diagram (a) Draw Logic Symbols
7411 triple 3-input AND gate
7427 triple 3-input NOR gate

11
4001 quad 2-input NOR
4011 quad 2-input NAND
4069 Hex inverter

12
4070 quad 2-input EX-OR
4071 quad 2-input OR
4081 quad 2-input AND

13
4023 triple 3-input NAND
4025 triple 3-input NOR
4073 triple 3-input AND

14
4075 triple 3-input OR

15
Viva-Voice Questions
1. Identify & write the IC Number of the following packages.
7400 4073 7408

………………………… ………………………… ………………………
2. Give the name of the packages used in the experiment.
3. DIP IC stands for?
4. How many gates are there in the following ICs.

a. 7400…………
b. 7408…………
c. 7404…………
d. 7432…………
e. 7486…………
5. How many gates are there in the following ICs.
a. 4081…………
b. 4073…………
c. 4069…………
d. 4081…………
Result
……………….………………..……………….……………..……………….………………..
……………….………………..……………….……………..……………….………………..

16
Verification of truth tables of Logic gates
Date: ................................
Aim
To Verify the truth tables of AND, OR, NOT, NAND, NOR and Ex-OR Gates
Apparatus & Components
1. Breadboard
2. +5V power supply
3. IC 7400 – 1No
4. IC 7402 – 1No
5. IC 7404 – 1No
6. IC 7408 – 1No
7. IC 7432 – 1No
8. IC 7486 – 1No
9. LED – 1No
10. Connecting wires
Theory
A digital circuit that can have one or more inputs and only one output is
known as logic gate.
Basic Logic Gates: The logic gates AND, OR and NOT are called basic logic
gates.
Universal Logic Gates: NAND and NOR gates are known as universal gates
because any logic function is implemented using only NAND or NOR gates.

17
(1) AND Gate:
• An AND gate performs logical multiplication, more commonly known as the
AND function.
• It has two or more inputs and one output.
• The standard logic symbol for a AND gate with two inputs A and B, and the
output Y is shown in fig. 2.1.
• The Boolean expression for AND function is Y = A ⋅ B.
A
Y = A⋅B
B
Fig. 2.1
• The output of AND gate is low if any one input is low or all the inputs are
low. The output of AND gate is high if all the inputs are high.
(2) OR Gate
• An OR gate performs logical addition, more commonly known as the OR
function.
• It has two or more inputs and one output.
• The standard logic symbol for an OR gate with two inputs A and B and the
output Y is shown in fig. 2.2.
• The Boolean expression for OR function is Y = A + B.
• The output of an OR gate is high if any one input is high or all inputs are high.
The output of an OR gate is low if all the inputs are low.
A
Y=A+B
B
Fig. 2.2
(3) NOT Gate
1. A NOT gate performs a basic logic function called inversion or
complementation.
2. It has only one input and output.
3. The standard logic symbol for a NOT gate is shown in fig. 2.3.
4. The Boolean expression for NOT function is Y = A .

18
5. If a high level is applied to the input of the NOT gate, a low level appears on the
output and vice versa.
A Y=A
Fig. 2.3
(4) NAND Gate
1. A NAND stands for NOT-AND.
2. The NAND gate has two or more inputs but only one output.
3. A NAND gate is nothing but AND gate followed by NOT gate.
4. The fig. 2.4(b) shows standard logic symbol of two input NAND gate.
5. The output of NAND gate is high if any one input is low or all inputs are low.
The output of NAND gate is low if all inputs are high.
Fig. 2.4(a) Fig. 2.4(b)

(5) NOR Gate
1. NOR stands for NOT-OR.
2. The NOR gate has two or more inputs but only one output.
3. A NOR gate is nothing but OR gate followed by NOT gate.
4. The fig. 2.5(e) shows standard logic symbol of two input NOR gate.
5. The output of NOR gate is low if any one input is high or all inputs are high. The
output of NOR gate is high if all the inputs are low.
Fig. 2.5(a) Fig. 2.5(b)

(6) Exclusive – OR Gate
1. The Exclusive OR is abbreviated as EX-OR or X-OR.
2. EX-OR gate has two inputs and one output.
3. Fig. 2.6(b) shows standard logic symbol for EX-OR gate.

19
4. The output of an EX-OR gate is high for odd number of 1’s at the input.
5. The output of an EX-OR gate is low for even number of 1’s at the input.
Fig. 2.6(a) Fig. 2.6(b)

Procedure
(1) AND gate

1. Insert IC 7408 at appropriate position on Breadboard.
2. Connect +5V to pin 14 and ground to pin 7.
3. Apply logic inputs for pin 1 & 2.
4. Connect the pin 3 to LED indicator.
5. Verify the truth tables by applying different combinations of inputs to the
input terminals.
6. Note the values of outputs for different combinations of inputs.
Note:
• When LED glows it indicates logic 1 otherwise logic 0.
• Verify the truth table for other AND gate.
(2) OR gate
input terminals.
Note:
• Verify the truth table for other OR gate.

20
(3) NOT gate

3. Apply the logic input for pin 1.
input terminals.
Note:
• Verify the truth table for other NOT gate.
(4) NAND gate
input terminals.
Note:
• Verify the truth table for other NAND gate.
(5) NOR gate
input terminals.

21
Note:
• Verify the truth table for other NOR gate.
(6) EX-OR gate
input terminals.
Note:
• Verify the truth table for other EX-OR gate.

22
Activity 1: To verify the truth table of AND gate
(a) PIN Diagram
(b) Truth Table (c) Observations
Inputs Output Inputs Output
A B Y A B Y
0 0 0 0 0
0 1 0 0 1
1 0 0 1 0
1 1 1 1 1
(d) Conclusions
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………

23
Activity 2: To verify the truth table of OR gate
(a) PIN Diagram
A B Y A B Y
0 0 0 0 0
0 1 1 0 1
1 0 1 1 0
1 1 1 1 1
(d) Conclusions
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………

24
Activity 3: To verify the truth table of NOT gate

(a) PIN Diagram
Input Output Input Output
A Y A Y
0 1 0
1 0 1
(d) Conclusions
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………

25
Activity 4: To verify the truth table of NAND gate
(a) PIN Diagram
A B Y A B Y
0 0 1 0 0
0 1 1 0 1
1 0 1 1 0
1 1 0 1 1
(d) Conclusions
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………

26
Activity 5: To verify the truth table of NOR gate

(a) PIN Diagram
A B Y A B Y
0 0 1 0 0
0 1 0 0 1
1 0 0 1 0
1 1 0 1 1
(d) Conclusions
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………

27
Activity 6: To verify the truth table of EXOR gate
(a) PIN Diagram
A B Y A B Y
0 0 0 0 0
0 1 1 0 1
1 0 1 1 0
1 1 0 1 1
(d) Conclusions
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………

28
1. Under what conditions the output of a two input AND gate is one?
2. When will the output of a NAND gate be 0?
3. Write the truth table for 3-input EX-OR gate.
4. Give the expression for for 3-input EX-OR gate.
5. Write the alternate names for the following logic gates.

a. AND ………………………………….
b. OR ………………………………….
c. NOT ………………………………….
d. EX-OR ………………………………….
e. EXNOR ………………………………….
Result
……………….………………..……………….……………..……………….………………..
……………….………………..……………….……………..……………….………………..

29
Realization of Logic functions using NAND/NOR
Date: ................................
Aim
To realize AND, OR, NOT, XOR functions using NAND gates only, NOR
gates only.
1. Breadboard
2. +5V power supply
3. IC 7400 – 1No
4. IC 7402 – 2No
5. LED – 1No
6. Connecting wires
Theory
• The NAND and NOR gates are known as universal gates, since any logic function can be
implemented using NAND and NOR gates.
• The NAND gate can be used to generate the NOT function, the AND function, the OR function
and the EX-OR function.
• An inverter can be made from a NAND gate by connecting all of the inputs together and
creating in effect, a single common input.
• An AND function can be generated using only NAND gates. It is generated by simply inverting
output of NAND gates; i.e., AB = AB .
• OR function is generated using only NAND gates. We know that Boolean expression for OR
gate is Y = A + B = A + B = A.B
• The above equation is implemented using 3 NAND gates.
• The NOR gate is also a universal gate, since it can be used to generate the NOT, AND, OR, and
EX-OR functions.
• An inverter can be made from a NOR gate by connecting all of the inputs together and creating,
in effect, a single common input

30
Activity 1: To realize NOT function using one NAND gate

(a) Circuit diagram
(b) Connection Diagram
A Y A Y
0 1 0
1 0 1
(d) Conclusions
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………

31
Activity 2: To realize AND function using Two NAND gates
(a) Circuit diagram

A B Y A B Y
0 0 0 0 0
0 1 0 0 1
1 0 0 1 0
1 1 1 1 1
(d) Conclusions
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………

32
Activity 3: To realize OR function using Three NAND gates

(a) Circuit diagram

33
A B Y A B Y
0 0 0 0 0
0 1 1 0 1
1 0 1 1 0
1 1 1 1 1
(d) Conclusions
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………
Activity 4: To realize EX-OR function using Four NAND gates
(a) Circuit diagram

34
A B Y A B Y
0 0 0 0 0
0 1 1 0 1
1 0 1 1 0
1 1 0 1 1
(d) Conclusions
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………

35
Activity 5: To realize NOT function using One NOR gates
(a) Circuit diagram
A Y A Y
0 1 0
1 0 1
(d) Conclusions
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………

36
…………………………………………………………………………….………………………………………………
Activity 6: To realize AND function using Three NOR gates

(a) Circuit diagram

37
A B Y A B Y
0 0 0 0 0
0 1 0 0 1
1 0 0 1 0
1 1 1 1 1
(d) Conclusions
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………
Activity 7: To realize OR function using Two NOR gates

(a) Circuit diagram (b) Connection Diagram

38
A B Y A B Y
0 0 0 0 0
0 1 1 0 1
1 0 1 1 0
1 1 1 1 1
(d) Conclusions
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………
Activity 8: To realize EX-OR function using Five NOR gates

(a) Circuit diagram

39
(b) Connection Diagram VCC
A B Y A B Y
0 0 0 0 0
0 1 1 0 1
1 0 1 1 0
1 1 0 1 1
(d) Conclusions
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………

40
1. Why NAND & NOR gates are called universal gates?
2. Draw the alternate logic symbols for NAND & NOR gates.
3. The bubbled NAND gate is also called?
4. The bubbled NOR gate is also called?
5. The minimum number of NAND/NOR gates required to realize EXNOR

gate is ……/………..
6. Realize EXNOR using minimum number of NAND/NOR gates.
7. Realize the boolean function Y = AB + CD using NAND gates.
Result
……………….………………..……………….……………..……………….………………..
……………….………………..……………….……………..……………….………………..

41
Verification of Demorgan’s Laws
Date: ................................
Aim
To verify Demorgan’s Laws using given digital trainer kit and given
TTL gates.
Theory
Augustus De-Morgan used the Boolean algebra and discovered two important
theorems known widely as De-Morgan’s theorems as follows.
1. First Theorem
The complement of sum is equal to the product of the individual
complements.
i.e., A + B = A. B
It really says that the complement of two or more variables ORed is the same
as the AND of the complements of each individual variable.
∴ A + B + C + D + ........ = A ⋅ B ⋅ C ⋅ D ⋅ ........
2. Second Theorem
The complement of product is equal to the sum of the individual
complements.
i.e., A.B = A + B
It really says that the complement of two or more variables ANDed is the
same as the OR of the complements of each individual variable.
∴ A ⋅ B ⋅ C ⋅ D ⋅ ........ = A + B + C + D + ........

42
Activity 1: To Verify Demorgan’s First Law using TTL gates

(a) Circuit diagram -1 (b) Circuit diagram - 2
(c) Connection Diagram - 1
(i) Truth Table (ii) Observations
A B A• B Y = A•B A B A• B Y = A•B
0 0 0 1 0 0 0
0 1 0 1 0 1 0
1 0 0 1 1 0 0
1 1 1 0 1 1 1

43
(d) Conclusions
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………
(d) Connection Diagram - 2
A B A B A+B A B A B A+B
0 0 1 1 1 0 0 1 1
0 1 1 0 1 0 1 1 0
1 0 0 1 1 1 0 0 1
1 1 0 0 0 1 1 0 0
(d) Conclusions
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………

44
Activity 2: To Verify Demorgan’s Second Law using TTL gates

(a) Circuit diagram -1 (b) Circuit diagram - 2
(c) Connection Diagram - 1
A B A+B Y=A+B A A+B Y=A+B
0 0 0 1 0 0 0
0 1 1 0 0 1 1
1 0 1 0 1 0 1
1 1 1 0 1 1 1

45
Conclusions:
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………
(d) Connection Diagram - 2
A B A B A•B A B A B A•B
0 0 1 1 1 0 0 1 1
0 1 1 0 0 0 1 1 0
1 0 0 1 0 1 0 0 1
1 1 0 0 0 1 1 0 0
Conclusions:
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………

46
1. State demorgans theorems.
2. What is min term and max term?
3. State the differences between SOP & POS?
4. What are the different methods to obtain minimal expressions?
5. What is K-map? Why it is used?
6. The complement of EXOR is ………………….
7. Simplify the following Boolean functions.

(a) A B + AB (b) A AB ⋅ BAB
Result
……………….………………..……………….……………..……………….………………..
……………….………………..……………….……………..……………….………………..
47
Construction of Half & Full Adder Circuits
Date: ................................
Aim
To Construct Half adder and full adder circuits and verify their functionality
Theory
• The most basic operation, is the addition of two binary digits

• The simple addition consists of four possible elementary operations, namely,
0+0=0
0+1=1
1+0=1
1 + 1 = 102
• The first three operations produce a sum whose length is one digit, but when
the last operation is performed sum is two digits. The higher significant bit of
this result is called a carry, and lower significant bit is called sum.
• The logic circuit which performs this operation is called a half adder.
• The half adder operation needs two binary inputs: augend and addend bits;
and two binary outputs: sum and carry.
• In multi digit addition we have to add two bits, along with the carry of
previous digit addition. Effectively such addition requires addition of three
bits. This is not possible with half adder. Hence half adders are not used in
practice.
• The circuit which performs addition of three bits (two significant bits and a
previous carry) is a full adder.
Procedure
1. Verify the gates.

2. Make the connections as per the circuit diagram.

48
3. Switch on VCC and apply various combinations of inputs according to truth

table.
4. Note down the output readings of sum and the carry bit for different
combinations of inputs.
Activity 1: To Construct Half adder circuit and verify its

functionality.
(a) Circuit diagram

49
(c) Truth Table (d) Observations
A B Carry Sum A B Carry Sum
0 0 0 0 0 0
0 1 0 1 0 1
1 0 0 1 1 0
1 1 1 0 1 1
Activity 1: To Construct full adder circuit and verify its

functionality.
(a) Circuit diagram
Conclusions:
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………

50

51
A B C Carry Sum A B C Carry Sum
0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 1
0 1 0 0 1 0 1 0
0 1 1 1 0 0 1 1
1 0 0 0 1 1 0 0
1 0 1 1 0 1 0 1
1 1 0 1 0 1 1 0
1 1 1 1 1 1 1 1
Conclusions:
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………
…………………………………………………………………………….………………………………………………

52
1. What is half adder?
2. What are the limitations of half adder?
3. Realize half adder using minimum number of NAND/NOR gates.
4. Write the truth table for half subtractor?
5. How you convert half adder into half subtractor?
6. Minimum number of NAND/NOR gates required to realize full adder

is…………./………….
7. What are the applications of adders?
Result
……………….………………..……………….……………..……………….………………..
……………….………………..……………….……………..……………….………………..

53
Flip Flops using Logic gates
Date: ................................
Aim
To construct clocked Flip Flops using Logic gates.

Apparatus
1. IC trainer kit
2. Connecting wires.
Theory
• In the sequential logic circuits the output not only depends on the present
inputs, but also on the previous outputs.
• Gates and flip-flops are required for constructing sequential logic circuits.
• Examples: Shift registers, counters, serial adder, RAM etc.
• The clock signal is generally a rectangular pulse train or square wave
• In synchronous system, the exact time at which any output can change states are
determined by clock.
• When the clock changes from 0 to 1, this is called the positive going transition
(PGT).
• Similarly when the clock goes from 1 to 0, this is the negative going transition
(NGT).
• The flip-flops using the clock signal are called the clocked flip-flops.
• Clocked flip-flops have a clock input that is typically labeled CLK or CP.
• Clocked flip-flops may be level clocked or edge triggered.
• The term edge triggered means that the flip-flop changes state either at the
positive edge (rising edge) or at the negative edge (falling edge) of the clock
pulse.
• Fig. 6.1 shows logic symbols of positive edge triggered flip-flops.
54
• Fig. 6.2 shows logic symbols of negative edge triggered flip-flops.
Fig. 6.1(a)
Fig. 6.2b)
Procedure
1. Place the ICs on breadboard. Give the connections as per the circuit diagram.
1. Connect VCC and ground to respective pins of IC trainer kit.
2. Connect the inputs to the input switches provided in the trainer kit.
3. Connect the outputs to the switches of LEDs.
4. Apply various combinations of inputs according to the truth table and
observe condition of LEDs.
Precautions
1. All the connections should be tight.

2. It should be care that the values of the components of the circuit is does not
exceed to their ratings (maximum value).

55
Activity 1: To construct RS Latch using NAND gates and verify

its truth table.
(a) Circuit diagram

S R Q n +1 S R Q n +1
x x * forbidden x x
0 0 Qn No change 0 0
0 1 0 Reset 0 1
1 0 1 Set 1 0
1 1 Qn No change 1 1

56
Activity 2: To construct RS Latch using NOR gates and verify

its truth table.
(a) Circuit diagram

State State
CLK S R Q n +1 CLK S R Q n +1
0 x x Qn No change 0 x x
1 0 0 Qn No change 1 0 0
1 0 1 0 Reset 1 0 1
1 1 0 1 Set 1 1 0
1 1 1 * forbidden 1 1 1

57
Activity 3: To construct SR flip-flop using NAND gates and
verify its truth table.
(a) Circuit diagram

State State
CLK S R Q n +1 CLK S R Q n +1
1 0 1 0 Reset 1 0 1
1 1 0 1 Set 1 1 0
1 1 1 * forbidden 1 1 1

58
Activity 4: To construct JK flip-flop using NAND gates and

verify its truth table.
(a) Circuit diagram

59

State State
CLK J K Q n +1 CLK J K Q n +1
1 0 1 0 Reset 1 0 1
1 1 0 1 Set 1 1 0
1 1 1 Qn Toggle 1 1 1
Activity 5: To construct D-flip flop using JK flip-flop and verify

its truth table.
(a) Circuit diagram

State State
CLK D Q n +1 CLK D Q n +1
0 x Qn No change 0 x
1 0 0 Reset 1 0
1 1 1 Set 1 1

60
Activity 6: To construct T-flip flop using JK flip-flop and verify

its truth table.
(a) Circuit diagram

State State
CLK T Q n +1 CLK T Q n +1
0 x Qn No change 0 x
1 0 0 Reset 1 0
1 1 Qn Toggle 1 1

61
Activity 7: To construct Master Slave JK flip-flop using NAND
gates and verify its truth table.
(a) Circuit diagram
(b) Truth Table
Inputs Output
CLK J Q State
K
0 x x Q0 No change
0 0 Q0 No change
0 1 0 Reset
1 0 1 Set
1 1 Q0 Toggle

62
1. In which flip-flop forbidden condition occurs?
2. What advantage does a JK flip-flop over SR flip-flop?
3. What is the difference between toggle and race around condition?
4. What are the applications of flip-flop?
5. How you convert SR flip-flop to JK flip-flop?
6. How you convert SR flip-flop to D flip-flop?
7. How you convert D flip-flop to T flip-flop and vice versa?
Result
……………….………………..……………….……………..……………….………………..
……………….………………..……………….……………..……………….………………..

63
Flip Flops using ICs
Date: ................................
Aim
1. To verify the truth table of CD 4013 Dual D flip Flop

2. To verify the functionality and truth table of 74L71 RS flip flop with
Preset and Clear
3. To verify the Truth table of JK FF using 7476 IC.
4. To construct D and T flip flops using 7476 and verify the truth tables.
1. IC trainer kit
2. IC 4013 – 1No
3. IC 7476 – 1No
4. IC 7404 – 1No
5. Connecting wires
6. Breadboard
7. +5V power supply
8. LED – 2No
9. Connecting wires
Theory
CD 4013 Dual D flip Flop

(a) General Description
The CD4013B dual D-type flip-flop is a monolithic complementary MOS
(CMOS) integrated circuit constructed with N- and P-channel enhancement mode
transistors. Each flip-flop has independent data, set, reset, and clock inputs and “Q”

64
and “Q” outputs. These devices can be used for shift register applications, and by
connecting “Q” output to the data input, for counter and toggle applications. The
logic level present at the “D” input is transferred to the Q output during the
positive-going transition of the clock pulse. Setting or resetting is independent of the
clock and is accomplished by a high level on the set or reset line respectively
(b) Features
• The CD 4013 is a CMOS chip.
• Wide supply voltage range: 3.0V to 15V
• Minimum supply voltage 6V
• Maximum supply voltage 15V
• High noise immunity: 0.45 VDD (typ.)
• Max current per output 15mA
• Maximum speed of operation 5MHz
(c) Applications
• Automotive • Data terminals • Instrumentation • Medical electronics • Alarm
system • Industrial electronics • Remote metering • Computers
IC 7476 Dual JK flip-flop
The 7476 contains two independent j-k flip-flops with individual J-K, clock,
present, and clear inputs. The 7476 is a positive-edge-triggered flip-flop. J-K input is
loaded into the master while the clock is high and transferred to the slave on the
high-to-low transition. For these devices the J and K inputs must be stable the clock
is high.
Procedure

65
Precautions
1. All the connections should be tight.

2. It should be care that the values of the components of the circuit is does not
exceed to their ratings (maximum value).

66
Activity 1: To verify the truth table of CD 4013 Dual D flip flop.

(a) PIN Diagram of CD 4013

67
(b) Logic symbol
INPUTS OUTPUTS INPUTS OUTPUTS
CL D Reset Set Q Q CL D Reset Set Q Q
0 0 0 0 1 0 0 0
1 0 0 1 0 1 0 0
× 0 0 Q Q × 0 0
× × 1 0 0 1 × × 1 0
× × 0 1 1 0 × × 0 1
× × 1 1 1 1 × × 1 1

68
Activity 2: To verify the functionality and truth table of 74L71

RS flip flop with Preset and Clear
(a) PIN Diagram of 54/74L71
(b) Logic symbol of 54/74L71

69
INPUTS OUTPUTS INPUTS OUTPUTS

PRE CLR CLK S R Q Q PRE CLR CLK S R Q Q
L H × × × H L L H × × ×
H L × × × L H H L × × ×
L L × × × H↑ H↑ L L × × ×
H H L L Q0 Q0 H H L L
H H H L H L H H H L
H H L H L H H H L H
H H H H forbidden H H H H
Activity 3: To Verify the Truth table of JK FF using 7476 IC

(a) PIN Diagram of 54/74L71

70
(b) Connection diagram

71

PRE CLR CLK J K Q n +1 PRE CLR CLK J K Q
L H × × × H L H × × ×
H L × × × L H L × × ×
L L × × × H* L L × × ×
H H ↓ L L Qn H H ↓ L L
H H ↓ H L H H H ↓ H L
H H ↓ L H L H H ↓ L H
H H ↓ H H Toggle H H ↓ H H
H H H × × Qn H H H × ×
Activity 4: Construct D flip flop using 7476 and verify the truth
tables
(a) Connection diagram

72
INPUTS OUTPUT INPUTS OUTPUT
Preset Clear D Clock Qn+1 Preset Clear D Clock Qn+1
1 1 0 0 1 1 0
1 1 1 1 1 1 1
Activity 5: Construct T flip flop using 7476 and verify the truth
tables
Preset Clear T Clock Q n +1 Preset Clear T Clock
1 1 0 Qn 1 1 0
1 1 1 Qn 1 1 1

73
Function of Asynchronous counters
Date: ................................
Aim
To construct and verify the function of Asynchronous counters

Apparatus
1. IC 7476 – 2No
2. Connecting wires
3. Breadboard
4. +5V power supply
5. LED – 3No
6. Connecting wires
Theory
A counter is a circuit consisting of a number of Flip Flop and gates working

together to count the number of clock pulses applied to its input. Such counters are
used in digital clocks, frequency counters, digital voltmeters, digital computers, and
numerous other applications.
Asynchronous counter or ripple counter is a serial counter. The clock input is
applied to only the first of the series of the Flip Flop. Clock pulses for the other Flip
Flop come from the preceding Flip Flop. Thus, the clock pulse ripples through the
circuit in a series fashion.
Procedure
1. Connections are made as per circuit diagram.

2. Clock pulses are applied one by one at the clock I/P and the O/P is
observed at QA, QB & QC for IC 7476.
3. Verify the Truth table.

74
Pin Diagrams
Activity 1: To construct and verify the function of 3-bit

asynchronous up counter.

75
CLK QC QB QA CLK QC QB QA
0 0 0 0 0 0 0
1 0 0 1 1 0 0
2 0 1 0 2 0 1
3 0 1 1 3 0 1
4 1 0 0 4 1 0
5 1 0 1 5 1 0
6 1 1 0 6 1 1
7 1 1 1 7 1 1
8 0 0 0 8 0 0
(d) Timing diagram

76
Activity 2: To construct and verify the function of 3-bit

asynchronous down counter.
CLK QC QB QA CLK QC QB QA
0 1 1 1 0 1 1
1 1 1 0 1 1 1
2 1 0 1 2 1 0
3 1 0 0 3 1 0
4 0 1 1 4 0 1
5 0 1 0 5 0 1
6 0 0 1 6 0 0
7 0 0 0 7 0 0
8 1 1 1 8 1 1

77
(d) Timing diagram

78
1. What is combinational logic circuit?
2. What is sequential logic circuit?
3. Define counter?
4. Which flip-flop is widely used in couners?
5. What is the meaning of negatively edged triggered flip-flop?
6. How many flip-flops are required to build mod 16 counter?
7. Mod 5 counter is also called?
Result
……………….………………..……………….……………..……………….………………..
……………….………………..……………….……………..……………….………………..

79
Function of decade counter using 7490 IC
Date: ................................
Aim
1. To construct and verify the function of decade counter using 7490 IC.
2. To change the modulus of the counter.
Apparatus
1. IC trainer kit
2. IC 7490 – 1No
3. IC 7411 – 1No
4. Connecting wires
5. Breadboard
6. +5V power supply
7. LED – 4No
8. Connecting wires
Theory
The most popular counter ICs from the 74xx series are the following
7490 1:10 counter which can be split into 1:2 and 1:5
All three ICs are based on JK flip flops and feature asynchronous reset
inputs. The IC 7490 is a Asynchronous Decade binary Counter.

80
Fig. 8.1 shows the basic internal structure of the IC 7490. In this circuit there
are four FLIP-FLOPS. In the figure FFA is a modulo-2 counter and FFB, FFC, and
FFD constitute a modulo-5 counter. The mod-2 and mod-5 counters can be used
independently or in combination.
Since the output from the divide-by-two section is not internally connected to
the succeeding stages, the devices may be operated in various counting modes.
(a) BCD Decade (8421) counter:
If the Q A output is connected to the input B and the pulses to be counted are
applied at the input A, then the circuit operates as a normal BCD counter.
(b) Divide by two and Divide by Five counters:
No external interconnections are required. The first flip-flop is used as a
binary element for the divide by two functions (A as the input and Q A as the
output). The B input is used to obtain binary divide-by-five operation at the Q D
output.
There are two reset inputs, R 1 and R 2 both of which are to be connected to
logic ‘1’ level for clearing all the FLIP-FLOPS. The two set inputs S1 and S2 are used
for setting the counter to 1001 when both connected to logic ‘1’ level.

81
Procedure
1. Check all the components for their working.

2. Insert the appropriate IC into the IC base.
3. Make connections as shown in the circuit diagram.
4. Verify the truth table and observe the outputs.
Activity 1: To construct and verify the function of decade

counter using 7490 IC.
(a) Circuit diagram

82

83
c) Truth Table
INPUTS OUTPUTS
R1 R2 S1 S2 QD Qc QB QA
H H L × L L L L
H H × L L L L L
× × H H H L L H
× L × L Count
Count
L × L ×
Count
L × × L
Count
× L L ×
d) Observations

84
Outputs
Clock pulse QD Qc QB QA
10

85
Activity 2: To change the modulus of the counter.

a) Circuit diagram of mod-2 counter
Observations:
Outputs
Clock Pulse QA

86
b) Circuit diagram of mod-5 counter
Note: To produce a standard divide-by-5 counter, we can disable the first flip-flop
above, and apply the clock input signal directly to pin 1 (CLKB with the output
signal being taken from pin 11 (QD) as shown.
Observations:
Outputs
Clock pulse QD Qc QB

87
b) Circuit diagram of mod-7 counter
Observations:
Outputs
Clock Pulse QD Qc QB QA

88
1) How many Flip-Flops are required to build decade counter?
2) Decade counter is also called?
3) The number of unused states in MOD-5 counter is ………
4) If two MOD-10 counters are cascaded, the resulting counter is called?
5) A MOD-2 counter followed by MOD-5 counter is called?
Result
……………….………………..……………….……………..……………….………………..
……………….………………..……………….……………..……………….………………..

89
Function of Synchronous Counters
Date: ................................
Aim
To realize 3-bit synchronous counter and verify truth table

Apparatus
1. IC trainer kit
Theory
The modulus of a counter is the number of output states it has. For example
mod-8 counter is having 8 different states (000 to 111). The number of flip-flops (n)
required to construct mod-N counter can be obtained from the following formula:
2 n −1 < N ≤ 2 n
Three flip-flops are required to construct mod-8 counter. A decade counter is
also called Mod-10 or ÷ 10 counter require 4 flip-flops. Any binary counter can be a
modulus counter where as the modulus counter need not be a binary counter.
The output signal frequency of mod-N counter is 1/ N th of the input clock
frequency. Hence that counter is also called ÷ N counter.
A counter having n flip-flops can have 2n output states i.e. it can count 2n
clock pulses (0 to 2n -1). The largest binary number that can be represented by an n-
bit counter has a decimal equivalent of ( 2n -1).

90
Comparison between Synchronous and Asynchronous Counters

Sl.No. Asynchronous Synchronous
1. In this type of counter flip-flops In this type there is no connection
are connected in such a way that between output of first flip-flop and
the output of first flip-flop drives clock input of the next flip-flop.
the clock for the next flip-flop.
2. All the flip-flops are not clocked All the flip-flops are clocked
simultaneously. simultaneously.
3. Logic circuit is very simple even Logic circuit is complex as number of
for more number of states. states increases.
4. Cost is low. Cost is high.
5. Its speed is lower than that of Its speed is higher than that of
synchronous counters. asynchronous counters.
6. These are also known as ripple or These are also known as parallel
serial counters. counters.
7. The speed of counters depends not The speed of this counter depends on
only on the width of clock pulse the width of clock pulses applied.
but also on the propagation delay
time of each flip-flop.
Procedure

2. Clock pulses are applied one by one at the clock I/P and the O/P is observed
at QA, QB & QC for IC 7476.
3. Verify the Truth table .

91
Activity 1: To realize 3-bit synchronous counter and verify truth
table.
a) Circuit diagram
b) Observations
Outputs
Clock pulse Qc QB QA
0
1
2
3
4
5
6
7
8
9

92
1. What are the differences betweenn synchronous and asynchronous
counters?
2. What are the disadvantages of ripple counters?
3. What are the advantages of synchronous counters?
4. List the disdvantages of synchronous counters over asynchronous.
5. Why MOD-8 counter is called ÷8 conter?
Result
……………….………………..……………….……………..……………….………………..
……………….………………..……………….……………..……………….………………..

93
Function of Up Down Counter
Date: ................................
Aim
To realize up down counter and verify truth table

Apparatus
1. IC trainer kit
Theory
(a) 3-Bit Up/Down Counter

• A 3-bit up/down counter whose operation is controlled by the U/ D control
input is shown in fig. 10(a).
• Counting sequence is given in the table as shown in fig. 10(b).
• The logic gates are used to allow either the non inverted or inverted output of
one flip-flop into the clock input of the following flip-flop, depending upon the
status of control inputs.
Fig. 10(a)
(b) Working
Case - I
When U/ D control signal is high, the lower AND gates (1 & 2) are disabled and
the upper AND gates (3 & 4) are enabled. In this mode the normal output of flip-

94
flops i.e. Q 0 and Q1 are connected to clock input of following flip-flops and the
counter acts as the up counter.
Case - II
When U/ D control signal is low, the upper AND gates (3 & 4) are disabled
and the lower AND gates (1 & 2) are enabled. In this mode the complementary
output of flip-flops i.e. Q0 and Q1 are connected to clock input of the following flip-
flop and the counter acts as down counter.
Clock Pulse Up-counter Down-counter
(CLK) Q2 Q1 Q0 Q2 Q1 Q0
0 0 0 0 0 0 0
1 0 0 1 1 1 1
2 0 1 0 1 1 0
3 0 1 1 1 0 1
4 1 0 0 1 0 0
5 1 0 1 0 1 1
6 1 1 0 0 1 0
7 1 1 1 0 0 1
8 0 0 0 0 0 0
(c) UP DOWN IC Counter
The 74193 is a 4-bit (mod -16) synchronous, presettable, up down binary
counter. It is a 16-pin DIP operating on +5V supply. It has a master reset (CLR), and
it can be reset to any desired count with the parallel load inputs. Basically, it
functions like any binary counter, except that is has two clock inputs, one for UP
counting, and the other for DOWN counting. LOAD is a control input to load data
into pins P0 – P3.

95
Activity 1: To realize up down counter using 74193 and verify
truth table.
(a) PIN diagram
(b) Logic Symbol

96
(c) Mode selection table
(d) Function Table
(e) Internal Circuit diagram

97
Activity 2: To realize Synchronous up down counter using IC
7476 and verify truth table
(a) Circuit diagram
(b) Truth table (c) Observations
Clock Pulse Up-counter Down-counter Clock Pulse Up-counter Down-counter

(CLK) Q2 Q1 Q2 Q1 (CLK) Q2 Q1 Q2 Q1
0 0 0 0 0 0
1 0 1 1 1 1
2 1 0 1 1 2
3 1 1 1 0 3
4 0 0 1 0 4

98
(d) Timing diagram

99
Activity 3: To realize Synchronous up down counter using IC

7476 and verify truth table
(a) Circuit diagram
Clock Pulse Up-counter Down-counter Clock Pulse Up-counter Down-counter

(CLK) Q2 Q1 Q2 Q1 (CLK) Q2 Q1 Q2 Q1
0 0 0 0 0 0
1 0 1 1 1 1
2 1 0 1 1 2
3 1 1 1 0 3
4 0 0 1 0 4

100
1. What is the name of IC 74193?
2. What is the use of master reset input?
3. List the features of IC 74193.
4. In asynchronous down counter which output of one flip-flop is given to the

clock of another flip-flop?
5. In countdown operation the clock is given to ……………………..pin.
6. How many JK flip-flops are there in IC 74776?
Result
……………….………………..……………….……………..……………….………………..
……………….………………..……………….……………..……………….………………..

101
Function of Shift Register
Date: ................................
Aim
To construct and verify the function of shift register

1. Breadboard
2. +5V power supply
3. IC 7495 – 1No
4. LED – 4No
5. Connecting wires
Theory
A register which is able to shift the binary information either from left to right
or right to left is called a shift register. This bit shifting is essential for certain
arithmetic and logical operations in micro computers. The shift register is used for
temporary storage of data. The shift registers can be built using R-S, J-K, or D flip-
flops.
A shift register capable of shifting binary data in one direction only is called
uni-directional shift register. A shift register that shifts the binary data by one bit to
the left is known as shift left register. A shift register that shifts the binary data by
one bit to the right is known as shift right register. A shift register capable of shifting
the binary data in both directions is called bi-directional shift register. If a shift
register has both shift and parallel load capabilities, it is referred to as universal shift
register. In shift registers data may be moved in and out serially or parallelly.
Depending upon this, shift registers may be classified as:
1. Serial In and Serial Out (SISO) shift register
2. Serial In and Parallel Out (SIPO) shift register
3. Parallel In and Serial Out (PISO) shift register

102
4. Parallel In and Parallel Out(PIPO) shift register

A SISO register introduces time delay in data transmission. The PISO shift
register is very useful in transferring data from a high speed device to a low speed
device. Similarly the SIPO shift register arrangement can transfer data from a low
speed device to a high speed device.
Activity 1: To construct and verify the function of SIPO shift

register.
Procedure
2. Apply the data serial i/p
3. Apply one clock pulse at clock 1(Right shift) observe this data at QA.
4. Apply the next data at serial i/p.
5. Apply one clock pulse at clock 2, observe that the data on QA will shift QB
and the new data applied will appear at QA.
6. Repeat steps 2 and 3 till all the 4 bits data are entered one by one into the shift
register.

103
Clock Serial I/P QA QB QC QD
1 0 0 × × ×
2 1 1 0 × ×
3 1 1 1 0 ×
4 1 1 1 1 0
Activity 2: To construct and verify the function of SISO shift

register.
Procedure
2. Load the shift with 4 bits of data one by one serially.
3. At the end of 4th clock pulse the first data ‘d0’ appears at QD.
4. Apply another clock pulse; the second data ‘dI’ appears at QD.
5. Apply another clock pulse; the third data appears at QD.
6. Application of next clock pulse will enable the 4th data ‘d3’ to appear at QD.
Thus the data applied serially at the input comes out serially at QD.

104
Clock Serial I/P QA QB QC QD
1 d0=0 0 × × ×
2 d1=1 1 0 × ×
3 d2=1 1 1 0 ×
4 d3=1 1 1 1 0=d0
5 × × 1 1 1=d1
6 × × × 1 1=d2
7 × × × × 1=d3

105
Activity 3: To construct and verify the function of PIPO shift
register.
Procedure
2. Apply the 4th bit data at A,B,C and D.
3. Apply one clock pulse at clock2 (Note: Mode control M=1).
4. The 4 bit data at A,B,C and D appears at QA, QB, QC and QD respectively.

106
Activity 4: To construct and verify the function of PISO shift

register.
Procedure
2. Apply the desired 4 bit data at A,B,C and D
3. Keeping the mode control M=1 apply one clock pulse. The data applied at
A,B,C and D will appear A QA,QB,QC and QD respectively.
4. Now mode control M=0. Apply clock pulses ane by one and aoserve the data
coming out serially at QD.

107
Activity 5: To construct and verify the function of Left shift
register.
(a) Procedure
1. Connections are made as per circuir diagram.

2. Apply the second data is made available at D and one clock pulse applied. The
dataappears at QD to QC and the new data appears at QD.
3. Step 3 is repeated until all the 4 bits are entered one by one.
4. At the end 4th clock pulse the 4 bits are available at QA,QB,QC and QD.
(b) Pin diagram (c) Truth table

108
1. What register?
2. List types of registers?
3. …………….shift register acts as ÷2 circuit
4. ……………shift register acts as ×2 circuit.
5. What are the applications of shift register?
6. What is ring counter?
7. How many clock pulses are required for the operation of the following
shift registers?
a. SISO :……………………
b. SIPO :……………………
c. PISO :……………………
d. PIPO :……………………
Result
……………….………………..……………….……………..……………….………………..
……………….………………..……………….……………..……………….………………..

109
Features of Encoders and Decoders
Date: ................................
Aim
To study the features of Encoders and Decoders
1. Breadboard
2. +5V power supply
3. IC 7408 – 1No
4. IC 7404 – No
5. IC 7432 – No
6. LED – 1No
7. Connecting wires
Theory
(a) Encoders
An encoder is a combinational logic circuit that receives digits (decimal, octal
etc), alphabets or special symbols and converts them to their respective binary
/BCD codes. In other words encoder may be said to be a combinational logic circuit
that performs the reverse operation of the decoder.
An encoder has m (≤ 2n ) input lines, only one of which is activated at a given
time, and produces an n-bit output code depending on which input is activated. Fig.
12.1 shows the block diagram of an encoder with m( ≤ 2 n ) inputs and n outputs.

110
Fig. 12.1
Examples:
1. 4 x 2 encoder
2. 8 x 3 encoder
3. 10 x 4 encoder
4. 16 x 4 encoder etc.
(b) Decoders
A decoder is a combinational circuit that converts binary information from n
input lines to a maximum of m ( ≤2n) output lines. In other words a decoder
converts binary data into other form viz. decimal, octal, hexadecimal etc.
Fig. 12.2 shows the block diagram of a decoder with n inputs and m ( ≤2n)
outputs. Examples: a) 2 x 4 decoder b) 3 x 8 decoder c) 4 x 10 decoder d) 4 x 16
decoder, etc.
Fig. 12.2

111
The decoders are used in the following applications:
1. Binary to octal conversion.
2. BCD to decimal conversion.
3. Hexadecimal to binary conversion.
4. BCD to gray code or gray to BCD conversion.
Procedure

112
Circuit diagram
(a) Truth Table (b) Observations
Inputs Outputs Inputs Outputs

A B Y0 Y1 Y2 Y3 A B Y0 Y1 Y2 Y3
0 0 1 0 0 0 0 0
0 1 0 1 0 0 0 1
1 0 0 0 1 0 1 0
1 1 0 0 0 1 1 1

113
Circuit diagram
(a) Truth Table (b) Observations

D0 D1 D2 D3 Y1 Y0 A B Y0 Y1 Y2 Y3
1 0 0 0 0 0 0 0
0 1 0 0 0 1 0 1
0 0 1 0 1 0 1 0
0 0 0 1 1 1 1 1

114
1. What is Decoder?
2. How you convert decoder into de-mux?
3. 1 x 4 demux acts as …………….decoder?
4. Where the encoders are widely used?
5. What are the applications of decoders?
Result
……………….………………..……………….……………..……………….………………..
……………….………………..……………….……………..……………….………………..

115
Multiplexers and De-multiplexers
Date: ................................
Aim
To study the features of Multiplexers and De-multiplexers
Theory
Multiplexer means many into one. A multiplexer is a combinational logic

circuit with many inputs but only one output. The multiplexer acts like a digitally
controlled multi-position switch.
A multiplexer with m inputs and 1 output is referred to as m ( 2n ) X 1
multiplexer. Examples: a) 4 x 1 multiplexer b) 8 x 1 multiplexer c) 16 x 1
multiplexer, etc.
The following are the important multiplexer applications:
1. The logic function generator.
2. The seven segment display multiplexer.
3. Digital counter with multiplexed display.
4. Data selector.
5. Parallel to serial convertor.
6. Waveform generator.
De-multiplexer means one into many. The de-multiplexer (De-MUX) performs
the reverse operation to a multiplexer. It takes data from one line and distributes it
over number of output lines, hence the name data distributor.
The following are the de-multiplexer applications:
1. De-multiplexers are used in
2. Boolean function implementation
3. Data transmission

116
4. Combinational logic circuit design

5. Generate enable signals in microprocessor systems
6. Communication systems
7. Arithmetic and Logical Units
8. Serial to Parallel converters
9. Decoder circuits
Procedure
(IC 74153)
1. The Pin [16] is connected to + Vcc.
2. Pin [8] is connected to ground.
3. The inputs are applied either to ‘A’ input or ‘B’ input.
4. If MUX ‘A’ has to be initialized, Ea is made low and if MUX ‘B’ has to
be initialized, Eb is made low.
5. Based on the selection lines one of the inputs will be selected at the
output and thus verify the truth table.
IC 74139
1. The inputs are applied to either ‘a’ input or ‘b’ input
2. The demux is activated by making Ea low and Eb low.
3. Verify the truth table.

117
Activity 1: To study the features of Multiplexers using logic

gates.
(a) Circuit diagram
Control inputs Output Control inputs Output

S1 S0 Y S1 S0 Y
0 0 D0 0 0
0 1 D1 0 1
1 0 D2 1 0
1 1 D3 1 1

118
Activity 2: To verify the truth table of MUX using IC 74153

(a) Pin diagram (b) Pin diagram

119
(c) Truth Table
Channel - A Channel - A
Inputs Select O/P Inputs Select O/P

lines lines
Ea Ioa I1a I2a I3a S1 S2 Za(v) Ea Ioa I1a I2a I3a S1 S2
1 × × × × × × 0 1 × × × × × ×
0 0 × × × 0 0 0 0 0 × × × 0 0
0 1 × × × 0 0 1 0 1 × × × 0 0
0 × 0 × 0 0 1 0 0 × 0 × 0 0 1
0 × 1 × 1 0 1 1 0 × 1 × 1 0 1
0 × × 0 × 1 0 0 0 × × 0 × 1 0
0 × × 1 × 1 0 1 0 × × 1 × 1 0
0 × × × 0 1 1 0 0 × × × 0 1 1
0 × × × 1 1 1 1 0 × × × 1 1 1

120
Activity 3: To study the features of De-multiplexers.

(a) Circuit diagram
Control inputs Outputs Control inputs Outputs

S1 S0 Y0 Y1 Y2 Y3 S1 S0 Y0 Y1 Y2 Y3
0 0 Din 0 0 0 0 0
0 1 0 Din 0 0 0 1
1 0 0 0 Din 0 1 0
1 1 0 0 0 Din 1 1

121
Activity 4: To verify the truth table of De-MUX using IC 74139
(a) Pin diagram
CHANNEL-A CHANNEL-A
Ea Sla S0a Y1a Y2a Y3a Y4a Ea Sla S0a Y1a Y2a Y3a Y4a
1 × × 1 1 1 1 1 × × 1 1 1 1
0 0 0 0 1 1 1 0 0 0 0 1 1 1
0 0 0 1 0 1 1 0 0 0 1 0 1 1
0 1 1 1 1 0 1 0 1 1 1 1 0 1
0 1 1 1 1 1 0 0 1 1 1 1 1 0

122
6. What is multiplexer?
7. The number of select lines for 16 x 1 mux is………….
8. What is demultiplexer?
9. Which combinational logic circuit is called data seletor (or) Universal

logic circuit?
10. Demultiplexer is also called data distributor
11. List the appl;ications of Multipleser?
Result
……………….………………..……………….……………..……………….………………..
……………….………………..……………….……………..……………….………………..

123
Hexadecimal Code on a 7 Segment Display
Date: ................................
Aim
Setup a circuit for displaying hexadecimal code on a 7 segment display.

Theory
(a) 7 segment display

Seven segment display is a device that can display decimal numbers and are
widely used in electronic clocks, electronic meters, digital display panels and a hand
full of applications where numerical data is is displayed.
Seven segment displays have seven segments which can be individually

controlled (ON/OFF) to display the desired number. Numbers from 0 to 9 can be
displayed using various combinations of the segments and in addition to this the
hexadecimal letters A to F can be also displayed using a seven segment display.
(b) Seven segment decoder / driver
Seven segment decoder / driver is a digital circuit that can decode a digital
input to the seven segment format and simultaneously drive a 7 segment LED
display using the decoded information.

124
To display the data, we have to convert it from BCD to 7-segment code. The
IC 7447 makes this process. It has four inputs called BCD inputs and seven outputs
to drive the display.
For common anode LED display, the decoders used are IC 7446, IC 74246, IC
7447, IC 74247 etc. They have active low, open collector outputs.
And for common cathode LED display, the ICs are IC 7448, IC 74248, IC 7449
etc. They have active high, open collector outputs.
(c) Working of the circuit
1) When BCD inputs from 0000 to 1001 are applied at the input terminals, the
IC produces equivalent outputs at its output terminals from a–g. The 7–seg display
is common anode type.
2) Suppose BCD input is DCBA = 0101. It is equivalent to decimal 5. This
input is converted into equivalent 7–seg code by the IC and its outputs abcdefg =
0100100. For the input DCBA = 1000, all segments of the display will glow to show
decimal 8 and outputs abcdefg = 0000000 and so on.
The below table shows the hexadecimal encoding for displaying the digits 0 –
9 and A – F.
Digit gfedcba abcdefg a b c d e f g
0 0×3F 0×7E on on on on on on off
1 0×06 0×30 off on on off off off off
2 0×5B 0×6D on on off on on off on
3 0×4F 0×79 on on on on off off on
4 0×66 0×33 off on on off off on on
5 0×6D 0×5B on off on on off on on
6 0×7D 0×5F on off on on on on on

125
7 0×07 0×70 on on on off off off off
8 0×7F 0×7F on on on on on on on
9 0×6F 0×7B on on on on off on on
A 0×77 0×77 on on on off on on on
b 0×7C 0×1F off off on on on on on
C 0×39 0×4E on off off on on on off
d 0×5E 0×3D off on on on on off on
E 0×79 0×4F on off off on on on on
F 0×71 0×47 on off off off on on on
Note: A 7 segment display contains seven light emitting diodes (LEDs)

Procedure
1. IC 7447/7448 and the 7–segment common anode LED display.

2. Identify them with their proper pin configurations.
3. Switch on the power supply of the circuit.
4. Connect different BCD inputs from 0000 to 1001 and note down the
corresponding output on the display.
5. Tabulate the readings.

126
PIN diagrams
(a) IC 7447
(b) IC FND 507/567

Pin FND 507/567
1 Segment E
2 Segment D
3 Common Anode
4 Segment C
5 Decimal point
6 Segment B
7 Segment A
8 Common Anode
9 Segment F
10 Segment G

127
Circuit diagram
IC 7446/is a 7–segment common anode LED display circuit.

128
Function Table
BCD 7-segment coded outputs Display

inputs output
a b c d e f g
0000 0 0 0 0 0 0 1
0001 1 0 0 1 1 1 1
0010 0 0 1 0 0 1 0
0011 0 0 0 0 1 1 0
0100 1 1 0 1 1 0 0

129
0101 0 1 0 0 1 0 0
0110 1 0 0 0 0 0 0
0111 0 0 0 1 1 1 1
1000 0 0 0 0 0 0 0
1001 0 0 0 1 1 0 0
Conclusions
1. When corresponding BCD inputs are applied from 0000 to 1001, we get
decimal output on the display from decimal 0 to decimal 9.
2. The tails of ‘6’ and ‘9’ are not displayed on the display.
3. To display the tails of ‘6’ and ‘9’ IC 74247 is required.
4. In common anode FND 507 type display, the anodes of all LEDs are
connected to a common line and connected to +5V regulated power supply.
The cathode of each LED segment is used as input from ‘a’ to ‘g’.

130
1. What is BCD?
2. List the examples for digital displays?
3. What is an LED.
4. What are the types of seven segment displays?
5. List seven segment decoder ICs.
6. List the applications of seven segment display.
Result
……………….………………..……………….……………..……………….………………..
……………….………………..……………….……………..……………….………………..

131
Tri-State Output Buffer
Date: ................................
Aim
To verify truth table and to study the operation of tri-state output buffer
1. Breadboard – 1No
2. IC 74125 – 1No
3. +5V power supply
4. LED – 1No
5. Connecting wires
Theory
(a) Tri-state buffer
A buffer circuit is one in which, the output follows the input. It has high input
impedance and low output impendence. A tri-state buffer can provide 3 output
states:
1. A low level state
2. A high level state
3. A high impedance state or open circuit state
We know that the transistor Q3 in totem pole is ON when output is high and Q4
is ON when output is low. In the high impedance state both transistors, Q3 and Q4
are turned OFF. As a result the output is open or floating it is neither low nor high.
(b) Circuit Symbols
Fig. 15.1(a) shows the graphic symbol of a tri-state buffer with active high
enable. It is also known as non-inverting tri-state buffer.
Fig. 15.1(b) shows the graphic symbol of a tri-state buffer with active low
enable. It is also known as inverting tri-state buffer.

132
Fig. 15.1(a) Fig. 15.1(b)

(c) IC DM74125
IC DM74125 is a Quad TRI-STATEÉ Buffers. This device contains four
independent gates each of which performs a non-inverting buffer function. The
outputs have the TRI-STATE feature. When enabled, the outputs exhibit the low
impedance characteristics of a standard TTL output with additional drive capability
at the high Logic level to permit the driving of bus lines without external pull-up
resistors. When disabled, both the output transistors are turned off presenting a
high-impedance state to the bus line. Thus the output will act neither as a significant
load nor as a driver. To minimize the possibility that two outputs will attempt to
take a common bus to opposite logic levels, the disable time is shorter than the
enable time of the outputs.
Procedure

133
Activity 1: To verify truth table and to study the operation of tri-

state output buffer
PIN diagram
Function Table
INPUTS OUTPUT
A C Y
L L L
H L H
X H Hi-Z
H=High logic level
L=Low logic level
X=either low or high logic level
Hi-Z=Tri-state (outputs are disabled)

134
7. What is tristate buffer?
8. List the types of tristate buffers?
9. List the applications of tristate buffers?
10. Draw the logic symbols of active low and acyive high tristate buffers?
11. The name of the IC 74125 is………………..
Result
……………….………………..……………….……………..……………….………………..
……………….………………..……………….……………..……………….………………..

135
Function of 4-bit magnitude comparator
Date: ................................
Aim
To study the function of 4-bit magnitude comparator

1. Bread board - 1No

2. IC 7585 - 1No
3. LEDs - 3No
4. +5V supply
5. Connecting wires
Theory
(a) Single Bit Comparator

In a single bit comparator, let us assume the bits to be compared are A and B.
Case-I
A is greater B if,
A = 1 and B = 0
From this statement we can write logic expression for A>B as,
X = (A > B) = AB …(1)
Case-II
A is equal to B if the following condition is satisfied
A = 1 and B = 1 (or) A = 0 and B = 0
The logic expression for A = B can be written as,
Y = (A = B) = A ⊕ B …(2)
Case-III

136
A is less than B if,

A = 0 and B = 1
Form this statement we can write logic expression for A<B as,
X = (A < B) = AB …(3)
Case-IV
The truth table for the comparator action is given in fig. 1.20(a).
Inputs Outputs
X Y Z
A B
A>B A=B A<B
0 0 0 1 0
0 1 0 0 1
1 0 1 0 0
1 1 0 1 0
Fig. 16.1(a)
Case-V
Using the logic expressions (1), (2) and (3), single bit comparator can be
realized using logic gates as shown in fig. 1.16(b).
Fig. 16.1(b)
(b) 4 Bit Comparator
Let us use the technique discussed above to develop a comparator to compare
two 4-bit binary numbers. Let us consider two 4 bit number A = A3 A2 A1 A0 and B =
B3 B2 B1 B0.
Case-I
A is greater B if,
1. A3 = 1 and B3 = 0 irrespective of the other bits.
or

137
2. A3 = B3 and A2 = 1, B2 = 0 irrespective of the values of A1, A0, B1 and B0.
or
1. A3 = B3 and A2 = B2 and A1 = 1 and B1 = 0, irrespective of A0 and B0.
or
2. A3 = B3 and A2 = B2 and A1 = B1 and A0 = 1 and B0 = 0
From these statement we can write logic expression for A>B as
X = (A > B) = A 3 B3 + A 3 ⊕ B 3 A 2 B 2 +
…(1)
A 3 ⊕ B 3 A 2 ⊕ B 2 A 1 B1 + A 3 ⊕ B 3 A 2 ⊕ B 2 A 1 ⊕ B1 A 0 B0
Case-II
A is equal to B if the following condition is satisfied
A3 = B3 and A2 = B2 and A1 = B1 and A0 = B0,
The logic expression for A = B can be written as,
Y = (A = B) = A 3 ⊕ B 3 ⋅ A 2 ⊕ B 2 ⋅ A1 ⊕ B1 ⋅ A 0 ⊕ B 0 …(2)
Case-III
A is less than B if,
1. A3 = 0 and B3 = 1 irrespective of the other bits.
Or
2. A3 = B3 and A2 = 0, B2 = 1 irrespective of the values of A1, A0, B1 and B0.
Or
3. A3 = B3 and A2 = B2 and A1 = 0 and B1 = 1, irrespective of A0 and B0.
Or
4. A3 = B3 and A2 = B2 and A1 = B1 and A0 = 0 and B0 = 1
From these statement we can write logic expression for A>B as
Z = (A < B) = A 3 B 3 + A 3 ⊕ B 3 A 2 B 2 + A 3 ⊕ B 3 A 2 ⊕ B 2 A 1 B1
+ A 3 ⊕ B 3 A 2 ⊕ B 2 A 1 ⊕ B1 A 0 B 0
Case-IV
Using logic expressions (1), (2) and (3), the logic diagram for 4 bit comparator
can be implemented as shown in fig. 16.2(a).
Case-V

138
To represent the above conditions in the form of truth table we required 256
combinations and hence a function table is shown in fig. 16.2(b).
*Note: The circuit for comparing two n-bit numbers has 22n entries in the truth table
and becomes too number some even with n=3.
Fig. 16.2(a)

139
Description of IC 7485
The74F85 is a 4-bit magnitude comparator that can be expanded to almost any
length. It compares two 4-bit binary, BCD, or other monotonic codes and presents
the three possible magnitude results at the outputs. The 4-bit inputs are weighed
(A0-A3) and (B0-B3) where A3 and B3 are the most significant bits. The operation of
the 74F85 is described in the function table, showing all possible logic conditions.
The upper part of the table describes the normal operation under all
conditions that will occur in a single device or in a series expansion scheme. In the
upper part of the table the three outputs are mutually exclusive. In the lower part of
the table, the outputs reflect the feed-forward conditions that exist in the parallel
expansion scheme.
The expansion inputs I A > B and I A > B and I A < B inputs of the next higher stage.
Stages can be added in this manner to any length, but a propagation delay penalty
of about 15ns is added with each additional stage. For proper operation, the
expansion inputs of the least significant word should word should be tied as
follows: I A > B = Low, I A > B = high, and I A < B = Low.

140
Activity 1 To study the function of 4-bit magnitude comparator

(a) Pin diagram
(b) Logic symbol

141
(c) Function table

142
1. What is digital comparator?
2. Which logic gate is used as basic comparator?
3. In 1bit comparartor how many times equality condition occurs?
4. What are the applications of digital and analog comparators?
5. Write the truth table for 2-bit comparator?
Result
……………….………………..……………….……………..……………….………………..
……………….………………..……………….……………..……………….………………..

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Introduction to the Breadboard

M.G.B Publications Digital Electronics Lab Practice

2. Make sure the power is off before you build anything.

6. Select a connection on your schematic and place a piece of hook-up wire

M.G.B Publications Digital Electronics Lab Practice

3. Leaving out wires.

4. Plugging wires into the wrong holes.

6. Modifying the circuit with the power on.

Example: Implementation of a Logic Circuit

Build a circuit to implement the Boolean function Y = A ⋅ B .

Hex Inverter: IC 7404 Quad 2 Input NAND: IC 7400

M.G.B Publications Digital Electronics Lab Practice

Fig. 0.3 The complete designed and connected circuit

M.G.B Publications Digital Electronics Lab Practice

Identification of Digital ICs

1. To identify the given digital ICs.

TTL 74XX Series ICs

Triple 3-input TTL gates

7410 Triple 3-input NAND gate

7411 Triple 3-input AND gate

7427 Triple 3-input NOR gate

M.G.B Publications Digital Electronics Lab Practice

CMOS 40XX Series ICs

4001 Quad 2-input NOR

4011 Quad 2-input NAND

4069 Hex inverter

4070 Quad 2-input EX-OR

4071 Quad 2-input OR

4081 Quad 2-input AND

Triple 3-input CMOS gates

4023 Triple 3-input NAND

4025 Triple 3-input NOR

4073 Triple 3-input AND

4075 Triple 3-input OR

M.G.B Publications Digital Electronics Lab Practice

7400 Quad 2-input NAND gate

(a) Pin Diagram (b) Logic Symbol

7402 Quad 2-input NOR gate

(a) Pin Diagram (b) Logic Symbol

M.G.B Publications Digital Electronics Lab Practice

7404 Hex inverter

(a) Pin Diagram (b) Logic Symbol

7408 Quad 2-input AND gate

(a) Pin Diagram (b) Logic Symbol

M.G.B Publications Digital Electronics Lab Practice

7432 Quad 2-input OR gate

(a) Pin Diagram (b) Logic Symbol

7486 Quad 2-input EXOR gate

(a) Pin Diagram (b) Logic Symbol

M.G.B Publications Digital Electronics Lab Practice

7410 triple 3-input NAND gate

(a) Pin Diagram (a) Draw Logic Symbols

7411 triple 3-input AND gate

(a) Pin Diagram (a) Draw Logic Symbols

7427 triple 3-input NOR gate

(a) Pin Diagram (a) Draw Logic Symbols

M.G.B Publications Digital Electronics Lab Practice

4001 quad 2-input NOR

(a) Pin Diagram (a) Draw Logic Symbols

4011 quad 2-input NAND

Et