CS304 Digital Systems Lab Manual Final

DIGITAL SYSTEMS LABORATORY -1-
LAB MANUAL
DIGITAL SYSTEMS
(CS-304)
III Sem (CS)
INDORE INSTITUTE OF SCIENCE

AND TECHNOLOGY, INDORE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG.

INDORE INSTITUTE OF SCIENCE AND

TECHNOLOGY, INDORE (M.P.)
DEPARTMENT OF
ELECTRONICS & COMMUNICATION
ENGINEERING
CERTIFICATE
This is to certify that Mr./Ms……………………………………………………………… with RGTU
Enrollment No. ..…………………………..has satisfactorily completed the course of experiments in
…………………….……………………………………………...………laboratory, as prescribed by Rajiv
Gandhi Proudhyogiki Vishwavidhyalaya, Bhopal for ……… Semester of the …………………….
Engineering Department during year 20….… − ....
Signature of
Faculty In-charge

DEPT.OF ELECTRONICS AND COMMN.

2021-22
LIST OF EXPERIMENTS
CLASS: III SEM (CSE)
SUBJECT: DIGITAL SYSTEMS LAB [CS-304]
Sl. No. Name of the Experiment Page No. Staff Sign.
01. To verify the operation of basic and derived TTL
gates using their truth tables.
02. To realize the basic and derived TTL gates using
universal (NAND and NOR) TTL gate by verifying
their truth tables.
03. To prove De Morgan’s theorem.
04. To verify the operation of binary half adder and full

adder using their truth tables.
05. To verify the operation of binary half subtractor
and full subtractor using their truth tables.
06. To verify the operation of 4-bit binary to gray and
gray to binary code converters using their truth
tables.
07. To verify the operation of 4-bit binary parallel
adder and subtractor.
08. To verify the operation of 4:1 line multiplexer and
1:4 line de-multiplexer using their truth tables.
09. To verify the operation of 4 line to 2 lines Encoder
and 2 line to 4 line Decoder by using their truth
tables.
10. To verify the operation of RS, JK, T and D Flip Flop
by using their truth tables.
11. To verify the operation of 4-bit binary parallel
adder and subtractor, using virtual labs.
12. To verify the operation of 4- bit synchronous/
asynchronous counter using JK flip flop, using
virtual labs.

EXPT.No. 1. VERIFICATION OF TTL GATE OPERATION USING TRUTH TABLES
AIM : To verify the operation of basic and derived TTL gates using their truth tables.
APPARATUS :
Sl. No. PARTICULARS RANGE / ID. No. QUANTITY

1 Digital Lab Trainer with Bread Board ST 2611 1
2 Quad -2 Input AND gate SN74LS08 1
3 Quad- 2 Input OR gate SN74LS32 1
4 Hex Inverter gate SN74LS04 1
5 Quad -2 Input NAND gate SN 74LS00 1
6 Quad -2 Input NOR gate SN 74LS02 1
7 Quad -2 Input Exclusive-OR gate SN 74LS86 1
8 Quad -2 Input Exclusive-NOR gate SN 74LS266 1
9 Connecting wires and patch cords ---- ----
THEORY :
Transistor-Transistor-Logic (TTL) is a family of high speed integrated circuits in which the input is
through a multi emitter transistor. The number of emitters in the input transistor is equal to the number of
required inputs (Fan-in). Multi emitter transistors have smaller values of capacitances when compared to
normal transistors due to smaller area. This helps in increasing the operating speed of the gates. TTL gates
are widely used in high speed applications and are considered to be a standard type of logic circuits with
which all other logic circuits are compared. TTL ICs have medium power dissipation, good noise immunity
and medium fan-out. Operating speeds of TTL ICs can be increased only at the cost of higher power
dissipation. TTL is a MSI logic circuit, hence not suitable where low power dissipation and high functional
packaging density is required. The basic TTL circuit is a NAND gate for positive logic. It is a saturated logic in
which the transistor enters into saturation region during operation.
The 74 xxx series represents the popular TTL ICs which are used in several applications. These ICs
are generally 14 pin ICs in which pin-7 is Ground connection and pin-14 is the power supply (VCC) which is
connected to +5V DC supply. The 74xxx series operates reliably in the temperature range of 0 to 70 C.
TTL has several sub-families classified on the basis of their operating speed and power dissipation,
they are :
(i) 74Lxxx : L stands for low power consumption
(ii) 74Hxxx : H stands for high speed
(iii) 74Sxxx : S stands for the Schottky diode used to increase the speed of operation
(iv) 74LSxxx : LS stands for Low power Schottky and is the most widely used TTL series due to its low
power dissipation and low propagation delay time

(v) 74HCxxx : HC stands for High Speed CMOS, this is also a widely used TTL series because of its high
speed operation and low power dissipation.
However, 74LSxxx is the most widely used family in almost all practical applications. Some of the basic and
derived TTL gates whose operations are being verified are:
(i) AND Gate: It is one of the multiple input basic logic gates whose output is HIGH when both inputs
are HIGH and output is LOW when any one of the inputs is LOW. The AND gate circuit
practically corresponds to the operation of two switches connected in series.
(ii) OR Gate : This is another multiple input basic TTL gate whose output is HIGH when any one of its
two inputs is HIGH and the output is LOW when both the inputs are LOW. The OR gate circuit
practically corresponds to the operation of two switches connected parallel.
(iii) NOT Gate : This is a single input and single output gate which has the ability to complement or
invert the input. Thus if the input is LOW then the output is HIGH and vice versa.
(iv) NAND Gate : A NAND gate is a NOT-AND or Negated-AND gate. This is a derived logic gate with
multiple inputs. A NAND gate is realized using a combination of an AND gate and a
NOT gate. The truth table of a NAND gate is exactly a complement of the AND gate
since it is negated AND gate. NAND gate is one of the universal gates.
(v) NOR Gate : A NOR gate is NOT-OR or Negated-OR gate. This is a derived logic gate with multiple
inputs. A NOR gate is realized using a combination of an OR gate followed by a NOT
gate. The truth table of a NOR gate is exactly a complement of the OR gate since it is
negated OR gate. NOR gate is another universal gate along with the NAND gate.
(vi) Ex-OR Gate : The Exclusive- OR or Ex-OR gate is a complex derived logic gate with multiple inputs.
This logic gate is realized using a combination of NOT, AND and OR gates so as to
generate the desired logical output. The Ex-OR gate practically corresponds to the
staircase lighting circuit.
(vii) Ex-NOR Gate : The Exclusive-NOR or Ex-NOR gate is a NOT-Ex-OR or Negated Ex-OR gate. It is
realized using an Ex-OR gate followed by a NOT gate or an inverter. The truth
table of the Ex-NOR gate is precisely the complement of the Ex-OR gate since it is
a negated Ex-OR gate.
PROCEDURE:
1. Select TTL mode on the Digital Lab Trainer kit using the Mode Selector toggle switch.
2. First identify proper pin numbers of the IC using the pin diagrams provided and mount the IC properly
on the bread board
3. Connect +5V DC power supply provided on digital lab trainer to Pin No. 14 (VCC) of the IC mounted on
the bread board and the ground point of digital lab trainer to Pin No. 7.
4. Connections are made as shown in Fig. (i) to verify the operation of the AND gate (¼ SN74LS08)
5. Power supply to the Digital Lab Trainer kit is turned ON using the POWER switch.
6. Inputs to the gate are taken from the 8-bit Data switches on the Digital trainer board (Any two out of
D0 to D7) and the ground points are connected to the Gnd point on the digital lab trainer board.
7. By changing the position of toggle switches, inputs to the gate (either 0 or 1) are fed as shown in the
truth table and the corresponding outputs are observed.
8. The logic gate outputs are observed and tabulated in the observation table by connecting the logic
gate output to any one of the display LEDs (0 to 7) provided on 8 Bit LED Display
9. Output of the logic gate is Logic-0 if display LED turns GREEN and Logic- 1 if it turns RED
10. Step Nos. 4, 5, 6, 7 and 8 are repeated for Figs. (ii) to (vii), i.e. for the other six logic gates.

11. Theoretical (Th) and Practical (Pr) values of logic gate output entries mentioned in the truth tables are
compared and verified for AND, OR, NOT, NAND, NOR, Ex-OR and Ex-NOR gates.
12. Identical entries of theoretical and practical output values will prove satisfactory operation.
CIRCUIT DIAGRAMS AND OBSERVATION TABLES:
Fig. (i) 2 INPUT AND Gate: Input A = Logic 0 or 1 Output , Y = (A . B)

Input B = Logic 0 or 1 Output Output
¼ SN74LS08 A B Y Y
1 Logic - 0 = 0 Volt ( Th.) ( Pr.)
A 3 Logic - 1 = 5 Volts 0 0 0
Output to LED
B 2
Y = (A.B) 0 1 0
1 0 0
The AND operation is represented by the operator “ . ” 1 1 1
Fig. (ii) 2 INPUT OR Gate: Output , Y = (A + B)

Output Output
¼ SN74LS32 A B Y Y
1 ( Th.) ( Pr.)
A 3
Output to LED 0 0 0
Y = (A+B)
B 2
0 1 1
1 0 1
The OR operation is represented by the operator “ + ” 1 1 1
Output , Y = A’
Fig. (iii) NOT Gate:
Output Output
A Y Y
1/6 SN74LS04 ( Th.) ( Pr.)
1 2 0 1
A Output to LED Y = A’
1 0
The NOT operation is represented by the operator “ ’ ”

Output , Y = (A . B)’
Fig. (iv) 2 INPUT NAND Gate :
Output Output
A B Y Y
( Th.) ( Pr.)
¼ SN74LS00
0 0 1
1
A 3
0 1 1
2 Output to LED Y = (A.B)’
B
1 0 1
1 1 0
A (A.B)
Y = (A . B)’
B
NAND Gate realization using AND & NOT gates

Fig. (v) 2 INPUT NOR Gate: Output , Y = (A + B)’

Output Output
¼ SN74LS02 A B Y Y
2 ( Th.) ( Pr.)
A 1
Output to LED Y = (A+B)’ 0 0 1
B 3
0 1 0
1 0 0
1 1 0
A (A+B)
Y = (A+B)’
B
NOR Gate realization using OR & NOT gates
Fig. (vi) 2 INPUT Ex-OR Gate: Output , Y = (A B)

Output Output
A B Y Y
¼ SN74LS86 ( Th.) ( Pr.)
1
A 3 0 0 0
B 2 Output to LED Y = (AB) 0 1 1
1 0 1
The Ex-OR operation is represented by the operator “” 1 1 0
A (A’. B)
B
Y =(AB) = (A’. B +A. B’) Ex-OR Gate realization using AND, OR & NOT gates
A
B (A.B’)
Fig. (vii) 2 INPUT Ex-NOR Gate : Output , Y = (AB)’ = (A B)

Output Output
A B Y Y
¼ SN74LS266 ( Th.) ( Pr.)
1 0 0 1
A 3
Output to LED Y = (AB)’ = (AB) 0 1 0
B 2
1 0 0
1 1 1
The Ex-NOR operation is represented by the operator “”
A (AB) Y = (AB)’ = (AB) Ex-NOR Gate realization using Ex- OR & NOT gates
B

PIN DIAGRAMS OF TTL ICs :
RESULTS :
Logical operation of all basic and derived TTL gates (AND, OR, NOT, NAND, NOR, Ex-OR and Ex-NOR gates)
have been verified by comparing the entries of theoretical and practical output values shown in their
corresponding truth tables.
VIVA QUESTIONS ANS ANSWERS:
1. What is the full form of TTL?

Answer01:
2. What is the IC number of HEX Inverter (NOT) gate?

Answer02:
3. What does the LS and HC stands for in the number of an IC?

Answer03:
4. Which pin is the ground pin of 2-input basic logic gate IC?
Answer04:
5. Which pin is the +Vcc pin in 14 pin 2-input basic logic gate IC?
Answer05:
6. List out the features of TTL ICs.

Answer06:

7. What is AND Gate?

Answer07:
8. What is OR Gate?
Answer08:
9. What is NOT Gate?

Answer09:
10. What is the IC number of 2-input OR gate?

Answer10:

DIGITAL SYSTEMS LABORATORY - 10 -
EXPT.No.2. REALIZATION OF BASIC AND DERIVED TTL GATES USING UNIVERSAL GATE
AIM : To realize the basic and derived TTL gates using universal (NAND and NOR) TTL gate by verifying their truth
tables.
APPARATUS :

3 Quad -2 Input NOR gate SN 74LS02 2
THEORY :
NAND and NOR gate are called as Universal gates because it is possible to realize basic logic gates
(AND, OR and NOT gate) and derived gates using universal gates.
PROCEDURE:
2. First identify proper pin numbers of the IC using the pin diagrams provided and mount the IC
properly on the bread board.
3. Connect +5V DC power supply provided on digital lab trainer to Pin No. 14 (VCC) of the IC mounted
on the bread board and the ground point of digital lab trainer to Pin No. 7.
4. Connections are made as shown in Fig. (i) to realize the logical operation of the NOT gate.
6. Inputs to the gate are taken from the 8-bit Data switches on the Digital trainer board (Any two out
of D0 to D7) and the ground points are connected to the Gnd point on the digital lab trainer board.
7. By changing the position of toggle switches, inputs to the gate (either 0 or 1) are fed as shown in
the truth table and the corresponding outputs are observed.
8. The outputs are observed and tabulated in the observation table by connecting the output to any
one of the display LEDs (0 to 7) provided on 8 Bit LED Display.
9. Output is Logic-0 if display LED turns GREEN and Logic- 1 if it turns RED.
10. Step Nos. 4, 5, 6, 7 and 8 are repeated for Figs. (ii) through (viii).
11. Theoretical (Th) and Practical (Pr) values of output entries mentioned in the truth tables are
compared and verified.


NAND GATE AS UNIVERSAL GATE:
Fig. (i) Realization of NOT Gate : Output , Y = (A)’
Input A = Logic 0 or 1
¼ SN74LS00 Input B = Logic 0 or 1 A Output Y Output Y
1 ( Th.) ( Pr.)
3
A Logic - 0 = 0 Volt 0 1
2
Output to LED
Logic - 1 = 5 Volts 1 0
Y =( A.A)’=(A)’
Fig. (ii) Realization of AND Gate : Output , Y = (A .B)

A B Output Y Output Y
¼ SN74LS00 ²∕₄ SN74LS00 ( Th.) ( Pr.)
1 4 0 0 0
A 3 6
B 2 5 Output to LED 0 1 0
Y = [(A. B)’]’= (A.B)
1 0 0
1 1 1
Output , Y = (A+B)
Fig. (iii) Realization of OR Gate :
Output Output
¼ SN74LS00 A B Y Y
1 3 A’ ( Th.) ( Pr.)
A 0 0 0
2
¾ SN74LS00
9
8 0 1 1
²∕₄ SN74LS00 10 Output to LED
4
6 1 0 1
B Y = (A’. B’)’= (A+B)
5 B’ 1 1 1
Fig. (iv) Realization of Ex-OR Gate :
²∕₄ SN74LS00
4 ⁴⁄₄SN74LS00
A 6
5
¼ SN74LS00
1 12 11
3
13
Output to LED
2
Y=(A’.B)+(A.B’) = (A B)
9 8
B 10
¾ SN74LS00 Output, Y = (A  B)
( Th.) ( Pr.)
0 0 0
0 1 1
1 0 1
1 1 0

NOR GATE AS UNIVERSAL GATE:

Fig. (v) Realization of OR Gate : Output, Y = (A +B)
¼ SN74LS02 ²∕₄ SN74LS02
2 5 ( Th.) ( Pr.)
A 1 4 0 0 0
3
Output to LED
B 6 0 1 1
Y = [(A+B)’]’ = (A+B)
1 0 1
1 1 1
Fig. (vi) Realization of NOT Gate : Output, Y = (A)’

Output Output
¼ SN74LS02 A Y Y
2
1 ( Th.) ( Pr.)
A 0 1
Output to LED
3
Y = (A)’ 1 0
Fig. (vii) Realization of AND Gate : Output, Y = (A . B)

¼ SN74LS02 Output Output
2
A B Y Y
1 A’
¾ SN74LS02 ( Th.) ( Pr.)
A
3 8 0 0 0
10
5 9 Output to LED 0 1 0
4
B Y = (A’+B’)’=(A. B)
6 B’ 1 0 0
²∕₄ SN74LS02
1 1 1
Fig. (viii) Realization of Ex-OR Gate :

⁴⁄₄SN74LS02 ¼ SN74LS02
11
A 13 2
1
B 12 Output to LED
3
Y =(A’.B)+(A.B’) = (A  B)
2 A’
1
A 8
10
3
¼ SN74LS02
5 9 Output, Y = (A B)
4
B ¾ SN74LS02
6 B’ A B Output Y Output Y
²∕₄ SN74LS02 ( Th.) ( Pr.)
0 0 0
0 1 1
1 0 1
1 1 0

RESULT :
Realization of all basic and derived TTL gates (AND, OR, NOT, and Ex-OR gates) have been verified by
comparing the entries of theoretical and practical output values shown in their corresponding truth tables.
VIVA QUESTIONS AND ANSWERS:
1. Why NAND and NOR gates are called as universal gates?

Answer01:
2. What is the IC number of 2-input NAND gate IC?

Answer02:
3. What is the IC number of 2-input NOR gate IC?

Answer03:
4. How many minimum numbers of NAND gates are required to realize AND gate?
Answer04:
5. How many minimum numbers of NOR gates are required to realize NAND gate?
Answer05:
6. How many minimum numbers of NAND gates are required to realize NOR gate?
Answer06:
7. How many minimum numbers of NAND gates are required to realize OR gate?
Answer07:
8. How many minimum numbers of NOR gates are required to realize AND gate?
Answer08:
9. How many minimum numbers of NOR gates are required to realize Ex-OR gate?
Answer09:
10. How many minimum numbers of NOR gates are required to realize Ex-NOR gate?
Answer10:

EXPT.No.3. PROVE DE MORGAN’S THEOREM
AIM : To prove De Morgan’s theorem.
APPARATUS :

THEORY :
Statement of De Morgan’s Theorem:
I Theorem: Complement of the sum is equal to the product of complements.
i.e. (A+B)’ = A’.B’
II Theorem: Complement of the product is equal to the sum of complements.
i.e. (A.B)’ = A’ + B’
Note: Here the sum and product refer to the Boolean sum and Boolean product i.e. AND & OR
respectively.
The generalized form of De Morgan’s theorem states that the complement of a function is obtained by
interchanging AND & OR operators and complementing each literal. De Morgan’s theorem can be
extended to three or more variables and can be generalized as follows: For N-variables,
De Morgan’s I Theorem: ( A + B + C + D + ∙∙∙∙∙∙ + N )’ = (A’. B’. C’. D’. ∙∙∙∙∙∙ .N’)
De Morgan’s II Theorem: ( A . B . C . D . ∙∙∙∙∙∙ . N )’ = (A’+ B’+ C’+ D’+ ∙∙∙∙∙∙ + N’)
PROCEDURE:
4. Left hand side and right hand side connections are made as shown in Fig. (i), to prove the De
Morgan’s I Theorem.
6. Inputs are taken from the 8-bit Data switches on the Digital trainer board (Any two out of D0 to D7)
and the ground points are connected to the Gnd point on the digital lab trainer board.
7. By changing the position of toggle switches, inputs (either 0 or 1) are fed as shown in the
observation table and the corresponding outputs are observed.

8. The gate outputs are observed and tabulated in the observation table by connecting the gate
output to any one of the display LEDs (0 to 7) provided on 8 Bit LED Display.
9. Output of the gate is Logic-0 if display LED turns GREEN and Logic- 1 if it turns RED.
10. Step Nos. 4, 5, 6, 7 and 8 are repeated for Fig. (ii) i.e. to prove the De Morgan’s II Theorem.
11. Theoretical (Th) and Practical (Pr) values of gate output entries mentioned in the observation tables
are compared and verified.

Input B = Logic 0 or 1 ¼ SN74LS08
Logic - 0 = 0 Volt
Logic - 1 = 5 Volts
Fig. (i) De Morgan’s I Theorem:

¼ SN74LS32 3/6 SN74LS04 1/6 SN74LS04
1 2 1
1 6 A 3
A 3 5
Output to LED 2 Output to LED
B 2 2/6 SN74LS04 Y2 = (A’.B’)
Y1 = (A+B)’ 3 4
B
Left Hand Side Right Hand Side
Output, Y1 = (A +B)’ Output, Y2 = (A’.B’)

A B Output Y1 Output Y1 Output Y2 Output Y2
(Th.) (Pr.) (Th.) (Pr.)
0 0 1 1
0 1 0 0
1 0 0 0
1 1 0 0
Fig. (ii) De Morgan’s II Theorem :

¼ SN74LS08 SN74LS04 2/6 SN74LS04
1/6 ¼ SN74LS32
1 2 1
1 A 3
A 3 5 6 Output to LED
Output to LED 2
B 2 Y4 = (A’+B’)
Y3 = (A.B)’
3 4
B
Left Hand Side Right Hand Side

Output, Y3 = (A.B)’ Output, Y4 = (A’+ B’)

A B Output Y3 Output Y3 Output Y4 Output Y4
(Th.) (Pr.) (Th.) (Pr.)
0 0 1 1
0 1 1 1
1 0 1 1
1 1 0 0
RESULT :
By comparing the entries of theoretical and practical output values shown in observation tables, the
column for Y1 and Y2 are same and column for Y3 and Y4 are same. Hence the De Morgan’s I and II theorem
is proved.
1. State DeMorgan’s first theorem.

Answer01:
2. State DeMorgan’s second theorem.

Answer02:
3. What is the use of DeMorgan’s theorem?

Answer03:
4. State duality theorem.

Answer04:
5. What is the dual relation of Boolean relation A + 0 = A?

Answer05:
6. What is the dual relation of Boolean relation A + A’= 1?

Answer06:

7. What is the dual relation of Boolean relation (A + B)’ = A’ . B’?

Answer07:
8. What are the uses of Boolean algebra rules?

Answer08:
9. What are Commutative laws?

Answer09:
10. State distributive law.

Answer10:

EXPT.No.4 VERIFICATION OF BINARY HALF ADDER AND FULL ADDER OPERATION USING
TRUTH TABLES
AIM : To verify the operation of binary half adder and full adder using their truth tables.
APPARATUS :

THEORY :
HALF ADDER:
Figure (i) shows the half adder diagram, is a combinational logic circuit with two inputs and two outputs.
The half adder circuit is designed to add two single bit binary numbers, A and B. It is the basic building
block for addition of two single bit numbers. This circuit has two outputs, CARRY-out (Cout) and SUM (S).
The SUM (S) output is the result of the Ex-OR gate and the CARRY-out (Cout) is the result of the AND gate.
FULL ADDER:
When multi bit numbers are to be added then the carry bit that is generated should also be taken care of.
Hence the 1-bit Full Adder has three inputs, the two single bit binary actual input bits A and B and an
additional CARRY-in (Cin) input bit and two outputs SUM (S) and CARRY-out (Cout). Full adder circuit which is
realize using two half adders and an OR gate as shown in figure (ii).
PROCEDURE:
4. Connections are made as shown in Fig. (i) to verify the operation of the half adder.
8. The outputs are observed and tabulated in the observation table by connecting the outputs (SUM
and CARRY) to any two of the display LEDs (0 to 7) provided on 8 Bit LED Display.

10. Step Nos. 4, 5, 6, 7 and 8 are repeated for Fig. (ii) i.e. Binary full adder.
11. Theoretical (Th) and Practical (Pr) values of output entries mentioned in the observation tables are

Input B = Logic 0 or 1
Input Cin= Logic 0 or 1
Logic - 0 = 0 Volt
Logic - 1 = 5 Volts
Fig. (i) Binary Half Adder:
¼ SN74LS86
1 3
A
Output to LED
B 2
S = (AB)
¼ SN74LS08
1
3
Output to LED
2 Cout = (A. B)
Outputs, S = (AB) & Cout = (A. B)

Output S Output S Output Output
A B (Th.) (Pr.) Cout Cout
(Th.) (Pr.)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Fig. (ii) Binary Full Adder :

¼ SN74LS86
1 2/4 SN74LS86
A 3 4
6
B 2 5
Output to LED
Cin 5
6 S = (A  B  Cin)
4
1
1 2/4SN74LS08 3
3 2
2 Output to LED
¼ SN74LS08 ¼ SN74LS32 Cout = [(A⊕B).Cin ] + (A.B)

= A.B + B. Cin + Cin. A

Output, S = (ABCin) Output, Cout = [(A⊕B).Cin]+(A.B)

A B Cin Output S Output S Output Cout Output Cout
(Th.) (Pr.) (Th.) (Pr.)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
RESULT :
Logical operations of half adder and full adder have been verified by comparing the entries of theoretical
and practical output values shown in their corresponding truth tables.
1. How many bits are required for addition using half adder?
Answer01:
2. What is the IC number of 2-input EX-OR gate IC?

Answer02:
3. How many half adders and OR gates are required to design a full adder?
Answer03:
4. How many input lines are in full adder and name them?
Answer04:

5. What will be SUM and CARRY output of half adder, when both the inputs bits are high?
Answer05:
6. What will be SUM and CARRY output of half adder, when any one of inputs bit is high?
Answer06:
7. What will be SUM and CARRY output of full adder, when any one of inputs bit is high?
Answer07:
8. What will be SUM and CARRY output of full adder, when all inputs bit are high?
Answer08:
9. What will be SUM and CARRY output of full adder, when any two inputs bit are high?
Answer09:
10. What are the output logical expression of SUM and CARRY of half adder, for input A & B?
Answer10:

EXPT.No.5 VERIFICATION OF BINARY HALF SUBTRACTOR AND FULL SUBTRACTOR

OPERATION USING TRUTH TABLES
AIM : To verify the operation of binary half subtractor and full subtractor using their truth tables.
APPARATUS :

THEORY :
HALF SUBTRACTOR
A logic circuit which is used for subtracting one single bit binary number from another single bit binary
number is called half subtractor. It has two inputs, A (minuend) and B (subtrahend) and two outputs, D
(difference) and Bo (borrow) as shown in figure (i). D indicates the difference of two inputs and Bo is the
output signal generated that informs the next stage that a “1” has been borrowed.
FULL SUBTRACTOR:
The full-subtractor as shown in figure (ii), is a combinational circuit which is used to perform subtraction
between two bits, taking into account that a “1” may have been borrowed by a lower significant stage. It
has three inputs, A (minuend) and B (subtrahend) and BORROW IN (BIN) and two outputs D (difference)
and BOUT (borrow out).
PROCEDURE:
4. Connections are made as shown in Fig. (i) to verify the operation of the half subtractor.

8. The outputs are observed and tabulated in the observation table by connecting the outputs
(DIFFERENCE and BORROW) to any two of the display LEDs (0 to 7) provided on 8 Bit LED Display.
9. Outputs are Logic-0 if display LED turns GREEN and Logic- 1 if it turns RED.
10. Step Nos. 4, 5, 6, 7 and 8 are repeated for Fig. (ii) i.e. Binary full subtractor.

Input BORin = Logic 0 or 1
Logic - 0 = 0 Volt
Logic - 1 = 5 Volts
Fig. (i) Binary Half Subtractor:
¼ SN74LS86
1 3
A
B 2 Output to LED
1 D = (AB)
1/6 SN74LS04
2 1
3
Output to LED
2
Bo = (A’. B)
¼ SN74LS08
Outputs, D = (AB) & Bo = (A’. B)
Output D Output D Output Output
A B (Th.) (Pr.) Bo Bo
(Th.) (Pr.)
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Fig. (ii) Binary Full Subtractor :
¼ SN74LS86
1 2/4 SN74LS86
A 3 4
6
B 2 5
Output to LED
Bin 3 5
2/6 SN74LS04 6 D = (A  B  Bin)
1 4 4
1/6 SN74LS04
1 3
2 1 2/4SN74LS08
3 2
2 Output to LED
¼ SN74LS08 ¼ SN74LS32 Bout = [(A⊕B)’.Bin ] + (A’.B)

= (A’. Bin +A’.B +B. Bin)

Output, D = (ABBin) Output, Bout = [(A⊕B)’.Bin]+(A’.B)

Output D Output D Output Output
A B Bin (Th.) (Pr.) Bout Bout
(Th.) (Pr.)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
RESULT :
Logical operations of half subtractor and full subtractor have been verified by comparing the entries of
theoretical and practical output values shown in their corresponding truth tables.
1. What is half subtractor?

Answer01:
2. What is full subtractor?

Answer02:
3. List out the 3-inputs of full subtractor.

Answer03:
4. List out the 2-outputs of Subtractor.

Answer04:

5. What will be the output conditions of half subtractor, when all the inputs are high?
Answer05:
6. What will be the output conditions of full subtractor, when all the inputs are high?
Answer06:
7. How many half subtractor and OR gate are required to realize full subtractor?
Answer07:
8. What is the borrow output expression of half subtractor, when inputs are assumed as A & B?
Answer08:
9. What is the difference output expression of half subtractor, when inputs are assumed as A & B?
Answer09:
10. What will be the output conditions of half subtractor, when all the inputs are Low?
Answer10:

EXPT.No.6 VERIFICATION OF BINARY TO GRAY AND GRAY TO BINARY CODE

CONVERTER OPERATION USING TRUTH TABLES
AIM : To verify the operation of 4-bit binary to gray and gray to binary code converters using their truth
tables.
APPARATUS :

THEORY :
Digital system can be designed to process data in discrete form only. Many physical system supply data
in continuous manner i.e. is analog data. So it is necessary to convert this analog information into digital
form by means of an analog to digital converter. Sometimes it is convenient to use gray code to
represent digital data converted from analog data. Gray code is also called unit code or reflected code. In
Gray Code generally each number differs from its succeeding and preceding code by one bit. Gray code is
not used in arithmetic operation but used to facilitate correction in digital communication.
Binary to Gray code conversion:
For a 4-bit binary code ( B3 B2 B1 B0 ) converted to 4-bit Gray code (G3 G2 G1 G0) the expressions are:
G0 = (B0) ⊕ (B1)
G1= (B1) ⊕ (B2)
G2 = (B2) ⊕ (B3)
G3 = B3
Gray to Binary code conversion:
For conversion of Gray to Binary, the expressions are:
B0 = (B1) ⊕ (G0)
B1 = (B2) ⊕ (G1)
B2 = (G2) ⊕ (G3)
B3 = G3
PROCEDURE:
2. First identify proper pin number of the IC using the pin diagram provided and mount the IC
4. Connections are made as shown in Fig. (i) to verify the operation of the binary to gray code
converter.
6. Inputs are taken from the 8-bit Data switches on the Digital trainer board (Any four out of D0 to D7)
and the ground point is connected to the Gnd point on the digital lab trainer board.

8. The outputs are observed and tabulated in the observation table by connecting the outputs to any
four of the display LEDs (0 to 7) provided on 8 Bit LED Display.
10. Step Nos. 4, 5, 6, 7 and 8 are repeated for Fig. (ii) i.e. Gray to binary code converter.

Input B0 = Logic 0 or 1
Logic - 0 = 0 Volt
Logic - 1 = 5 Volts
Fig. (i) Binary to Gray code converter:
(MSB)B3 1 ¼ SN74LS86 Output to LED

3 G3 (MSB)
B2 2
Output to LED
2/4 SN74LS86 G2
4
6
Output to LED
B1 5
G1
9 ¾ SN74LS86
8
Output to LED
(LSB)B0 10
G0 (LSB)
Outputs, G3 = B3; G2 = [(B2)⊕(B3)]; G1= [(B1)⊕(B2)]; G0 = [ (B0)⊕(B1)]

Output Output Output Output Output Output Output Output
B3 B2 B1 B0 G3 G3 G2 G2 G1 G1 G0 G0
(Th.) (Pr.) (Th.) (Pr.) (Th.) (Pr.) (Th.) (Pr.)
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

Input G0 = Logic 0 or 1
Logic - 0 = 0 Volt
Logic - 1 = 5 Volts
Fig. (ii) Gray to Binary code converter :
¼ SN74LS86
(MSB)G3 1 Output to LED
3
2
Output to LED B3 (MSB)
G2
2/4 SN74LS86 B2
4
5 6
G1 Output to LED
B1
9 ¾ SN74LS86
10 8 Output to LED
(LSB)G0
B0 (LSB)
Outputs, B3 = G3; B2 = [(G2)⊕(B3)]; B1= [(G1)⊕(B2)]; B0 = [ (G0)⊕(B1)]
Output Output Output Output Output Output Output Output
G3 G2 G1 G0 B3 (Th.) B3 B2 (Th.) B2 B1 (Th.) B1 B0 (Th.) B0
(Pr.) (Pr.) (Pr.) (Pr.)
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0
PIN DIAGRAM OF TTL IC :
RESULT :
Logical operations of 4- bit binary to gray and gray to binary code converters have been verified by
comparing the entries of theoretical and practical output values shown in their corresponding truth tables.

1. Gray code is also called as?

Answer01:
2. How many Ex-OR gates are required to realize 4-bit Gray to binary code conversion?
Answer02:
3. Which code is not used in arithmetic operation?

Answer03:
4. Which type of code is a gray code?

Answer04:
5. Which class the gray code belongs?

Answer05:
6. How many Ex-OR gates are required to realize 4-bit binary to gary code conversion?
Answer06:
7. What are the binary outputs (B3, B2, B1,B0) obtained when gray inputs (G3,G2,G1,G0) are 0001 ?
Answer07:
8. What are the binary outputs (B3, B2, B1,B0) obtained when gray inputs (G3,G2,G1,G0) are 0010 ?
Answer08:
9. What are the gray outputs (G3,G2,G1,G0) obtained when binary inputs (B3, B2, B1,B0) are 0001 ?
Answer09:
10. What are the gray outputs (G3,G2,G1,G0) obtained when binary inputs (B3, B2, B1,B0) are 0010 ?
Answer10:

EXPT.No.7. VERIFICATION OF BINARY PARALLEL ADDER AND SUBTRACTOR OPERATION
AIM : To verify the operation of 4-bit binary parallel adder and subtractor.
APPARATUS :

3 4-bit binary parallel adder/ subtractor SN74LS83 1
THEORY :
BINARY PARALLEL ADDER
The functional diagram of a 4-bit binary adder IC 7483 is shown in figure (i). Input data A (A 4 A3 A2 A1 ) and
B (B4 B3 B2 B1 B0) are the two 4-bit inputs, and carry out (COUT), output data S (S4, S3, S2, S1) is the 5-bit
output. Binary adder accepts two 4-bit binary numbers as inputs and produces a 5-bit binary number as
output.
When MODE select , M = 0; figure (i) performs as 4-bit binary parallel adder.
BINARY PARALLEL SUBTRACTOR:
For finding the difference between two 4-bit binary numbers, separate subtractors are not used, but
adders are used as subtractors. For this purpose 1’s or 2’s complement representation of binary numbers
are used. Generally 2’s complement method is used for subtraction. For 2’s complement, a ‘1’ is added to
the 1’s complement of a number.
When MODE select , M = 1; figure (i) performs as 4-bit binary parallel subtractor.
PROCEDURE:
3. Connect +5V DC power supply provided on digital lab trainer to Pin No. 14 (VCC) of the IC SN74LS86
mounted on the bread board and the ground point of digital lab trainer to Pin No. 7.
4. Connect +5V DC power supply provided on digital lab trainer to Pin No.5 (VCC) of the IC SN74LS83
mounted on the bread board and the ground point of digital lab trainer to Pin No. 12.
5. Connections are made as shown in Fig. (i) to verify the operation of the 4-bit parallel adder keeping
MODE select, M = 0 (connecting to Gnd point).
7. Inputs are taken from the 8-bit Data switches on the Digital trainer board (Four inputs D0 to D3 as
input data A and next four inputs D4 to D7 as input data B) and the ground point is connected to the
Gnd point on the digital lab trainer board.

9. The outputs are observed and tabulated in the observation table by connecting the outputs to any
five of the display LEDs (0 to 7) provided on 8 Bit LED Display.
11. Step Nos. 5, 6, 7 and 8 are repeated for Fig. (i) i.e. to verify the operation of the 4-bit parallel
subtractor keeping MODE select, M = 1 (connecting to +5V DC power supply point).

Input A1 = Logic 0 or 1 Input B1 = Logic 0 or 1 Input M = Logic 0 or 1
Input A2= Logic 0 or 1 Input B2= Logic 0 or 1
Input A3 = Logic 0 or 1 Input B3 = Logic 0 or 1 Logic - 0 = 0 Volt
Input A4= Logic 0 or 1 Input B4= Logic 0 or 1 Logic - 1 = 5 Volts
Logic - 0 = 0 Volt Logic - 0 = 0 Volt

Logic - 1 = 5 Volts Logic - 1 = 5 Volts
Fig. (i) 4-Bit Binary Parallel Adder/Subtractor:
Vcc
5
A4 1
14 C4
A3 3 Output Carry
Input
Data”A” A2 8
15 S4
A1 10 7
1/4 SN74LS86 4 2 S3 Output
1
3 L Data”S”
B4 2 16 S 6 S2
2/4 SN74LS86
8
3 9 S1
B3 4 4
6
5
Input 3/4 SN74LS86
Data”B”
B2 9 7
8
10
4/4 SN74LS86
B1 12 11
11
13 13 12
Mode Select (M)

M = 0 (Addition)
M = 1 (Subtraction)

4 - BIT BINARY PARALLEL ADDER
Inputs Outputs
Sl.No. Cout S4 S3 S2 S1 Cout S4 S3 S2 S1
A4 A3 A2 A1 B4 B3 B2 B1 M (Th.) (Th.) (Th.) (Th.) (Th.) (Pr.) (Pr.) (Pr.) (Pr.) (Pr.)
1 0 1 0 1 0 0 1 1 0 0 1 0 0 0
2 0 1 1 0 0 1 0 0 0 0 1 0 1 0
3 1 1 1 1 0 1 0 1 0 1 0 1 0 0
4 1 1 0 0 0 0 1 1 0 0 1 1 1 1
4 - BIT BINARY PARALLEL SUBTRACTOR
Inputs Outputs
Sl.No. Cout S4 S3 S2 S1 Cout S4 S3 S2 S1
A4 A3 A2 A1 B4 B3 B2 B1 M (Th.) (Th.) (Th.) (Th.) (Th.) (Pr.) (Pr.) (Pr.) (Pr.) (Pr.)
1 0 1 0 1 0 0 1 1 1 1 0 0 1 0
2 0 1 1 0 0 1 0 0 1 1 0 0 1 0
3 1 1 1 1 0 1 0 1 1 1 1 0 1 0
4 1 1 0 0 0 0 1 1 1 1 1 0 0 1
RESULT :
By comparing the entries of theoretical and practical output values shown in observation tables, the logical
operation of 4-bit binary parallel adder/subtractor have been verified.
1. What is binary parallel adder?

Answer01:
2. What is the IC number of 4-bit binary parallel adder/subtractor?

Answer02:
3. How many full adders are required to perform the operation of 4-bit parallel adder and subtractor?
Answer03:

4. What is the IC number of 2-input Ex-OR gate?

Answer04:
5. Which pin is the ground and Vcc pin of 4-bit parallel adder and subtractor IC?
Answer05:
6. Which type of arithmetic operation performed by parallel adder /subtractor IC when mode select is 1?
Answer06:
7. Which type of arithmetic operation performed by parallel adder /subtractor IC when mode select is 0?
Answer07:
8. What is the disadvantage of parallel adder /subtractor?

Answer08:
9. What is the solution for ripple carry delay in parallel adder/subtractor?

Answer09:
10. What is the principle of carry look ahead adder?

Answer10:

EXPT.No.8. VERIFICATION OF MULTIPLEXER AND DEMULTIPLEXER OPERATION USING

TRUTH TABLES
AIM : To verify the operation of 4:1 line multiplexer and 1:4 line demultiplexer using their truth tables.
APPARATUS :

2 Dual 4-line to 1-line Multiplexer SN 74LS153 1
3 Dual 1-line to 4-line Demultiplexer SN 74LS155 1
THEORY :
MULTIPLEXER
Multiplexer is combinational circuit which selects binary information from one of the many input lines and
directs it to a single output line that is why a multiplexer is also called a data selector. It is used for parallel
to serial conversion of data. The selection of particular input line is controlled by a set of lines called
selection lines. Normally for ‘n’ selection lines, there are 2n input lines. Selection lines bit combination
determines which input is selected.
4:1 MULTIPLEXER:
Dual 4 to 1 line multiplexer has 4 input lines 1 output line and 2 select lines as shown in figure (i) and pin
out diagram in figure (iii). It has 4 line inputs (1C0, 1C1, 1C2, 1C3) and only one output Y1. G1 is the strobe
input (active low). A and B are the select lines; these lines select one out of four inputs at the output.
Strobe (also called as enable) input can be used to expand multiplexer ICs with a larger number of inputs.
Fig.(i) Logic diagram of Dual 4-line to 1-line Multiplexer

1:4 DEMULTIPLEXER:
Demultiplexer performs the reverse operation of multiplexer. Demultiplexer is a combinational circuit
which transmits single input information to one of the many output lines, selected by select lines is called
Demultiplexer. It is also known as data distributor. Demultiplexer is used for serial to parallel conversion of
data. Dual 1 to 4 line demultiplexer shown in figure (ii) and pin out diagram in figure (iv), consist one input
line Data C1 and four output lines (1Y0, 1Y1, 1Y2,1 Y3) and two select lines A and B.
Fig.(ii) Logic diagram of Dual 1-line to 4-line Demultiplexer
PROCEDURE:
3. Connect +5V DC power supply provided on digital lab trainer to Pin No. 16 (VCC) of the IC
SN74LS153 mounted on the bread board ,the ground point of digital lab trainer to Pin No. 8 and
strobe pin (G1) Pin No. 01 which is active low is connected to ground Gnd point.
4. Connections are made as shown in Fig. (iii) to verify the operation of the 4 line to 1 line multiplexer.
6. Inputs are taken from the 8-bit Data switches on the Digital trainer board (Any four inputs of D 0 to
D7 as input data 1C0, 1C1, 1C2, 1C3) and the ground point is connected to the Gnd point on the
digital lab trainer board.
observation table and the corresponding output is observed.
8. The output is observed and tabulated in the observation table by connecting the output to any of
the display LEDs (0 to 7) provided on 8 Bit LED Display.
10. To verify the operation of the 1 line to 4 line Demultiplexer, make the connections as shown in Fig.
(iv).

11. Connect +5V DC power supply provided on digital lab trainer to Pin No. 16 (VCC) of the IC
SN74LS155 mounted on the bread board ,the ground point of digital lab trainer to Pin No. 8 and
strobe pin (G2) Pin No. 14 which is active low is connected to ground Gnd point.
13. Input is taken from the 8-bit Data switches on the Digital trainer board (Any one input of D0 to D7
as input data is C2) and the ground point is connected to the Gnd point on the digital lab trainer
board.
observation table and the corresponding output is observed.
15. The outputs (2Y0 2Y1 2Y2 2Y3) are observed and tabulated in the observation table by connecting
the outputs to any four of the display LEDs (0 to 7) provided on 8 Bit LED Display.

Input 1C0 = Logic 0 or 1 Input A = Logic 0 or 1
Input 1C1 = Logic 0 or 1 Input B = Logic 0 or 1
Input 1C2 = Logic 0 or 1 Input 1G’ = Logic 0
Input 1C3 = Logic 0 or 1
Logic - 0 = 0 Volt Logic - 0 = 0 Volt
Logic - 1 = 5 Volts Logic - 1 = 5 Volts
Fig. (iii) 4 to 1 line Multiplexer:

Vcc Gnd
1C0 16 8
6
7
1C1 5 4
Data Input MUX
1 7 1Y
Lines 1C2 4
5 Output
1C3 3 3 Line
1 14 2
strobe
1G’ A B
Select lines
Inputs Output Output
Data Inputs Select Inputs 1Y 1Y
1C0 1C1 1C2 1C3 B A (Th.) (Pr.)
1 0 0 0 0 0 1
0 1 0 0 0 1 1
0 0 1 0 1 0 1
0 0 0 1 1 1 1

Input C2 = Logic 1
Input G2 = Logic 0
Logic - 0 = 0 Volt
Logic - 1 = 5 Volts
Fig. (iv) 1 to 4 line Demultiplexer:
Vcc Gnd
16 8
Data Input C2 15 9 2Y0
strobe G2 14 10 2Y1 Output
74155 Lines
Select B 3 11 2Y2
lines A 13 2Y3
12
Inputs
Data Select Outputs
Input Inputs
2Y0 2Y0 2Y1 2Y1 2Y2 2Y2 2Y3 2Y3
C2 B A (Th.) (Pr.) (Th.) (Pr.) (Th.) (Pr.) (Th.) (Pr.)
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

Vcc 2G’ A 2C0 2C1 2C2 2C3 2Y Vcc C2 G2 A 2Y3 2Y2 2Y1 2Y0
16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9
74153 74155
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
1G’ B 1C3 1C2 1C1 1C0 1Y Gnd C1 G1 B 1Y3 1Y2 1Y1 1Y0 Gnd
74153 Dual 4-line to 1-line Multiplexer 74155 Dual 1-line to 4-line Demultiplexer
RESULT :
By comparing the entries of theoretical and practical output values shown in observation tables, the logical
operation of 4-line to 1-line multiplexer and 1-line to 4-line demultiplexer have been verified as shown in
their corresponding truth tables.

1. What is the IC number of 4x1 multiplexer?

Answer01:
2. What is the IC number of 1x4 demultiplexer?

Answer02:
3. What is multiplexer ?
Answer03:
4. What is the use of multiplexer?

Answer04:
5. What do you understand by 2n x 1 multiplexer?

Answer05:
6. What is demultiplexer?
Answer06:
7. What is the use of demultiplexer?

Answer07:
8. What do you understand by 1 x 2n demultiplexer?

Answer08:
9. What is the function of selection line in multiplexer?

Answer09:
10. What is the function of Strobe pin?

Answer10:

EXPT.No.9. VERIFICATION OF ENCODER AND DECODER OPERATION USING TRUTH

TABLES
AIM: To verify the operation of 4 line to 2 line Encoder and 2 line to 4 line Decoder by using their truth tables.
APPARATUS:

2 Quad -2 Input AND gate SN 74LS08 1
3 Quad -2 Input OR gate SN 74LS32 2
THEORY :
ENCODER:
An encoder is a device used to change a signal (such as a bit stream) or data into a code. The code may
serve any of a number of purposes such as compressing information for transmission or storage,
encrypting or adding redundancies to the input code, or translating from one code to another. This is
usually done by means of a programmed algorithm, especially if any part is digital, while most analog
encoding is done with analog circuitry. Figure (i) shows the logic diagram of 4 line to 2 line priority
encoder. D0 D1 D2 D3 are the input lines and outputs are Y0 Y1 and V. Output V will be 1, when atleast
one input is one i.e. V = D0 + D1 + D2 + D3.
DECODER:
A decoder is a device which does the reverse of an encoder, undoing the encoding so that the original
information can be retrieved. The same method used to encode is usually just reversed in order to decode.
Figure (ii) shows the 2 line to 4 line decoder. Here the two inputs (A0 A1) are decoded into four outputs
(D0 D1 D2 D3).
PROCEDURE:
4. Connections are made as shown in Fig. (i) to realize the logical operation of the 4 line to 2 line
encoder.
6. Inputs to the gate are taken from the 8-bit Data switches on the Digital trainer board (Any four out

two of the display LEDs (0 to 7) provided on 8 Bit LED Display.
10. Step Nos. 4, 5, 6, 7 and 8 are repeated for Fig. (ii) i.e. to realize the operation of 2 line to 4 line
decoder.

Input D0 = Logic 0 or 1
Logic - 0 = 0 Volt
Logic - 1 = 5 Volts
Fig. (i) 4 line to 2 line Encoder:
D3 D2 D1 D0
1/4 SN74LS08
1 1
1/6 SN74LS04 1/4 SN74LS32
3
2 2 1
2 3 Output to LED
1 Y0 = D1.D2’+D3
1/4 SN74LS32
3 Output to LED
2 Y1 = D2 + D3
4 2/4 SN74LS32
4/4 SN74LS32
6 12
5
9 3/4 SN74LS32 11 Output to LED
13
8 V = D0 +D1+D2+D3
10
Outputs, Y1 = D2 + D3; Y0 = D1.D2’+D3; V = D0 +D1+D2+D3

Output Output Output Output Output V Output V
D3 D2 D1 D0 Y1 Y1 Y0 Y0 (Pr.) (Th.) (Pr.)
(Th.) (Pr.) (Th.)
0 0 0 1 0 0 1
0 0 1 0 0 1 1
0 1 0 0 1 0 1
1 0 0 0 1 1 1

Fig. (ii) 2 line to 4 line Decoder:
Input A0 = Logic 0 or 1
Input A1 = Logic 0 or 1
Logic - 0 = 0 Volt
Logic - 1 = 5 Volts
1/6 SN74LS04 1/4 SN74LS08

1 2 1
A0 3
2/6 SN74LS04 Output to LED
A1 2 D0 = A0’. A1’
3 4 2/4 SN74LS08
4
6
5 Output to LED
9 3/4 SN74LS08 D1 = A0. A1’
8
10
Output to LED
12 D2= A0’.A1
11
Output to LED
13
4/4 SN74LS08
D3 = A0.A1
Outputs, D3 = A0.A1; D2 = A0’.A1; D1 = A0.A1’; D0 = A0’.A1’

A1 A0 Output Output Output Output Output Output Output Output
D3 D3 D2 D2 D1 D1 D0 D0
(Th.) (Pr.) (Th.) (Pr.) (Th.) (Pr.) (Th.) (Pr.)
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
PIN DIAGRAMS OF TTL GATE ICs :
RESULTS :
Realization of 4 line to 2 line encoder and 2 line to 4 line decoder have been verified by comparing the
entries of theoretical and practical output values shown in their corresponding truth tables.
1. What is an encoder?
Answer01:

2. What do you understand by “n” – to – “m” encoder?

Answer02:
3. How many input and output lines are in Octal-to-Binary encoder?

Answer03:
4. How many input and output lines are in Decimal-to-BCD encoder?

Answer04:
5. What is a priority encoder?

Answer05:
6. What is a decoder?
Answer06:
7. Is there another combinational logic circuit which performs the function of decoder?
Answer07:
8. How many input and output lines are in Binary-to-Octal decoder?

Answer08:
9. What are the applications of decoder?

Answer09:
10. How many input and output lines are in Binary-to-Hexadecimal decoder?
Answer10:

EXPT.No.10. VERIFICATION OF RS, JK, T AND D FLIP FLOP OPERATION USING TRUTH
TABLES
AIM : To verify the operation of RS, JK, T and D Flip Flop by using their truth tables.
APPARATUS :

3 Dual –Master Slave JK Flip Flop SN 74LS76 1
THEORY :
A flip flop is a binary cell capable of storing one bit of information. A flip-flop circuit can maintain a binary
state indefinitely until directed by an input signal to switch states. Simple flip-flop consists of two cross-
coupled inverting elements-transistors or NAND, or NOR gates. Clocked device are specially designed for
synchronous (time-discrete) system, this cause the flip flop to either change or retain its output signal
based upon the values of the input signals at the transition of clock signal. Some flip flops change output
on the rising edge or on the trailing edge of the clock. As per the applicability in both asynchronous and
clocked sequential systems, flip-flops are further divided into: S-R, D, T, and J-K types.
CLOCKED R-S FLIP FLOP:

The clocked RS flip-flop consists of basic flip-flop circuit along with two additional NAND gates and a
clock signal. The clock signal act as an enable signal for the two inputs. If the clock =0 then the logic
circuit will not respond to the input signal. Only when the clock = 1 (rising or falling edge) the logic circuit
is enabled and respond to the applied input signals. The diagram is shown in figure (i).
J-K FLIP FLOP:

In SR flip flop, the condition S=R=1 is not permitted, output is in indeterminate state and this difficulty is
overcome by JK flip flop. Figure (ii) shows the diagram of one of the Dual- Master Slave JK flip flop. When J
= K= 1, output will complement or toggle. In this circuit, preset (PR) and clear (CLR) are active-low
(indicated by bubbles). When PR = ground, output Q is “set” (1) and CLR=ground, output Q will be
“reset”(0). In each case outputs Q and Q’ are complement to each other. PR and CLR pins are independent
of J and K inputs.
D-F LIP FLOP:

D-flip-flops are used to eliminate the indeterminate state that occurs in RS Flip-flop. The D input goes
directly into the J1 input and the complement of the D input goes to the K1 input as shown in figure (iii).
The D input is sampled during the occurrence of a clock pulse. If it is 1, the flip-flop is switched to the set
state (unless it was already set). If it is 0, the flip-flop switches to the clear state.

T- FLIP FLOP:
T flip-flop is the single input version of JK flip-flop. This modified form of JK flip-flop is obtained by
connecting both inputs J1 and K1 together as shown in figure (iv). This flip-flop has only one input along
with clock pulse.
These flip-flops are called T flip-flops because of their ability to complement its state (i.e.) Toggle. So they
are called as Toggle flip-flop.
PROCEDURE:
3. Connect +5V DC power supply provided on digital lab trainer to Pin No. 14 (VCC) of the IC 7404, IC
7400 and Pin No. 5 (Vcc) of the IC 7476 mounted on the bread board and the ground point of
digital lab trainer to Pin No. 7 of the IC 7404, IC 7400 and Pin No. 13 of the IC 7476.
4. Connections are made as shown in Fig. (i) to realize the logical operation of the SR Flip Flop.
6. Inputs to the gate are taken from the 8-bit Data switches on the Digital trainer board (Any two out
7. Input to the CLOCK terminal (Low to High transition) is taken from the 8-bit Data switches on the
Digital trainer board (Any one out of D0 to D7).
two of the display LEDs (0 to 7) provided on 8 Bit LED Display.
11. To realize the operation of JK Flip Flop, make the connections as shown in Fig. (ii).
12. Input to the preset (PR) and clear (CLR) terminal (active low) is taken from the 8-bit Data switches
on the Digital trainer board (Any two out of D0 to D7).
13. Step Nos. 5, 6, 7, 8, 9 and 10 are repeated for Fig. (ii).
14. Step Nos. 4, 5, 6, 7, 8, 9, 10 and 12 are repeated for Fig. (iii) and (iv) to realize the logical operation
of T-Flip Flop and D-Flip Flop.


Fig. (i) Clocked R-S Flip Flop :
1/4 SN74LS00 3/4 SN74LS00
1 9
Input S = Logic 0 or 1 3 8
Input R = Logic 0 or 1 S 2 10 Output to LED
Input CLOCK = Logic 0 to 1 CLOCK Q
4 6 12
Logic - 0 = 0 Volt 11 Output to LED
Logic - 1 = 5 Volts
R 5 13
2/4 SN74LS00 4/4 SN74LS00 Q’
Output Output Output Output

CLOCK S R Q Q Q’ Q’ Comments
(Th.) (Pr.) (Th.) (Pr.)
Low to 0 0 0 1 No Change
High
Low to 0 1 0 1 RESET
High
Low to 1 0 1 0 SET
High
Low to 1 1 1 1 Invalid
High
Fig. (ii) JK Flip Flop :
Input PR1 = Logic 0 or 1 Vcc Gnd

Input CLR1 = Logic 0 or 1
Input Clk1 = Logic 0 to 1 5 13
Input J1 = Logic 0 or 1 Clk 1 1
Input K1 = Logic 0 or 1
PR 1 2
Logic - 0 = 0 Volt 15
Output to LED
Logic - 1 = 5 Volts 7476 Q1
CLR 1 3
14
Output to LED
J1 4
Q 1’
16
K1

Clk 1 PR1 CLR 1 J1 K1 Q1 Q1 Q1’ Q1’ Comments
(Th.) (Pr.) (Th.) (Pr.)
Low to No Change
High 1 1 0 0 0 1
Low to RESET
High 1 1 0 1 0 1
Low to SET
High 1 1 1 0 1 0
Low to Toggle or
High 1 1 1 1 1/0 0/1
Complement

Fig. (iii) T- Flip Flop :

Vcc Gnd
Input PR1 = Logic 0 or 1
Input T = Logic 0 or 1 Clk 1 1
Logic - 0 = 0 Volt PR 1 2
15
Logic - 1 = 5 Volts Output to LED
7476 Q1
CLR 1 3
14
Output to LED
4
J1 Q 1’
T
16
K1

Clk 1 PR 1 CLR 1 T Q1 Q1 Q1’ Q1’ Comments
(Th.) (Pr.) (Th.) (Pr.)
Low to 1 1 0 No Change
High 0 1
Low to 1 1 1 Toggle
High
0/1 1/0
Fig. (iv) D - Flip Flop :
Vcc Gnd
Input PR1 = Logic 0 or 1
Input D = Logic 0 or 1 Clk 1 1
Logic - 0 = 0 Volt PR 1 2
15
Logic - 1 = 5 Volts Output to LED
7476 Q1
CLR 1 3
14
Output to LED
D J1 4 Q 1’
16
1 2 K1
1/6 SN74LS04

Clk 1 PR 1 CLR 1 D Q1 Q1 Q1’ Q1’ Comments
(Th.) (Pr.) (Th.) (Pr.)
Low to
High
1 1 0 0 1 RESET
Low to
High 1 1 1 1 0 SET

PIN DIAGRAMS OF TTL AND, OR AND NOT GATE ICs :
7476 Dual Master Slave JK Flip Flop
RESULT :
Logical operations of RS, JK, T and D Flip Flop have been verified by comparing the entries of theoretical
and practical output values shown in their corresponding truth tables.
1. What is flip-flop?
Answer01:
2. What is the function of flip-flop?

Answer02:
3. List out the types of flip-flop.

Answer03:

4. What do you understand by invalid output condition in clocked S-R flip-flop using NAND gates?
Answer04:
5. What do you understand by RESET condition in clocked S-R flip-flop using NAND gates?
Answer05:
6. What do you understand by SET condition in clocked S-R flip-flop using NAND gates?
Answer06:
7. What are the input conditions for which output of J-K flip flop toggles?
Answer07:
8. What is D flip flop?

Answer08:
9. What is T flip-flop?
Answer09:
10. What does edge-triggered means?

Answer10:

EXPT.No.11. IMPLEMENTATION AND VERIFICATION OF BINARY PARALLEL ADDER /

SUBTRACTOR OPERATION USING VIRTUAL LABS
AIM : To implement and verify the operation of 4-bit binary parallel adder/ subtractor using virtual labs.
REQUIREMENT FOR USE OF VIRTUAL LAB :
Sl. No. PARTICULARS REQUIRED

Windows7 or 10
1 Desktop Computer/Laptop
Operating System
2 Google Chrome Internet Browser -
3 www.vlab.co.in Web Site address
Introduction to virtual labs:

Virtual Labs is an MHRD initiative, Govt of India, which aims at making the experiments done in
Engineering Colleges available in a Virtual form, to all the college students as an adjunct facility to the
physical labs. These labs provide an opportunity to the students to perform these simulated experiments,
read the theory and improve their understanding of the subject.
There are 1800+ Virtual Experiments bundled in 180 + labs spread across 9 domains available for the users
of Virtual Labs. Some of these labs have software dependencies such as Java, Icedtea plugin, Adobe Flash
and Java3D to run the simulations.
OBJECTIVES:
1) To provide remote-access to simulation-based Labs in various disciplines of Science and Engineering.
2) To enthuse students to conduct experiments by arousing their curiosity. This would help them in
learning basic and advanced concepts through remote experimentation.
3) To provide a complete Learning Management System around the Virtual Labs where the students/
teachers can avail the various tools for learning, including additional web-resources, video-lectures,
animated demonstrations and self-evaluation.
THEORY :
BINARY PARALLEL ADDER
The functional diagram of a 4-bit binary adder IC 7483 is shown in figure (i). Input data A (A 4 A3 A2 A1 ) and
B (B4 B3 B2 B1 B0) are the two 4-bit inputs, and carry out (COUT), output data S (S4, S3, S2, S1) is the 5-bit
output. Binary adder accepts two 4-bit binary numbers as inputs and produces a 5-bit binary number as
output.
When MODE select , M = 0; figure (i) performs as 4-bit binary parallel adder.
BINARY PARALLEL SUBTRACTOR:

For finding the difference between two 4-bit binary numbers, separate subtractors are not used, but
adders are used as subtractors. For this purpose 1’s or 2’s complement representation of binary numbers
are used. Generally 2’s complement method is used for subtraction. For 2’s complement, a ‘1’ is added to
the 1’s complement of a number.
When MODE select , M = 1; figure (i) performs as 4-bit binary parallel subtractor.

Fig. (i) 4-Bit Binary Parallel Adder/Subtractor:

Vcc
5
A4 1 Output Carry
14 C4
A3 3
Input
Data”A” A2 8
15 S4
A1 10 7
1/4 SN74LS86 4 2 S3 Output
1
B4 3 L Data”S”
2 16 6 S2
S
2/4 SN74LS86
8 9 S1
B3 4 4
6
Input 5
3/4 SN74LS86
Data”B” 9
B2 8 7
10
4/4 SN74LS86
B1 12 11
11 13 12
13
Mode Select (M): M = 0 (Addition); M = 1 (Subtraction)

Truth Table of 4 - BIT BINARY PARALLEL ADDER
Inputs Outputs
Sl.No.
A4 A3 A2 A1 B4 B3 B2 B1 Mode(M) C4 S4 S3 S2 S1
1 0 1 0 1 0 0 1 1 0 0 1 0 0 0
2 0 1 1 0 0 1 0 0 0 0 1 0 1 0
3 1 1 1 1 0 1 0 1 0 1 0 1 0 0
4 1 1 0 0 0 0 1 1 0 0 1 1 1 1
4 - BIT BINARY PARALLEL SUBTRACTOR
Inputs Outputs
Sl.No.
A4 A3 A2 A1 B4 B3 B2 B1 Mode(M) C4 S4 S3 S2 S1
1 0 1 0 1 0 0 1 1 1 1 0 0 1 0
2 0 1 1 0 0 1 0 0 1 1 0 0 1 0
3 1 1 1 1 0 1 0 1 1 1 1 0 1 0
4 1 1 0 0 0 0 1 1 1 1 1 0 0 1
STEPS FOR SELECTING EXPERIMENT FROM VIRTUAL LAB:
1. Open virtual lab website using google chrome/Mozilla web browser (www.vlab.co.in)
2. Select “ Electronics and Communication” area.
3. Select “ Digital Electronics Circuits Lab (IIT Kharagpur)” under area of “ Electronics and Communication”
area.

4. Click on “List of Experiments.”
5. Select the experiment “Analysis and synthesis of arithmetic expressions using Adders/Subtractors”.
6. Select Simulation.
PROCEDURE USING VIRTUAL LAB:

1. At first click on the Browse Block button
2. Next, drag the Adder block and drop it onto the bread board.
3. Next, drag the Ex-OR-Gate block and drop it onto the bread board.

4. Next, drag the Bus block and drop it onto the bread board.

5. Next, drag the output block and drop it onto the bread board.
6. Next, make a connection from switch A to A3 of the Adder..

7. Next, make a connection from switch H to 1st pin of 7486.

8. Next, make a connection from C0 of Adder to 2nd pin of 7486.
9. Next, make a connection from 2nd pin of 7486 to 5th pin of 7486.
10. Next, make a connection from 5th pin of 7486 to 9th pin of 7486.
11. Next, make a connection from 9th pin of 7486 to 12th pin of 7486.
12. Next, make a connection from 11th pin of 7486 to B3 of Adder.
14. Next, make a connection from 3rd pin of 7486 to B0 of Adder.
16. Next, make a connection from S1 of Adder to 2nd LED.
17. Next, switch on the Vcc of Adder & 14th pin of 7486(for Vcc) and switch on the ADD/SUB then switch on the
A0,A1,A2 of Adder & switch on the B0,B2 of 7486.

18. Next, switch on the Vcc of Adder & 14th pin of 7486(for Vcc) and switch on the ADD/SUB then switch
on the A0,A2 of Adder & switch on the B0,B1,B2 of 7486.
19. Next, switch on the Vcc of Adder & 14th pin of 7486(for Vcc) and switch off the ADD/SUB then switch
on the A0,A1,A2,A3 of Adder & switch on the B0,B1,B2,B3 of 7486.

20. Next, switch on the Vcc of Adder & 14th pin of 7486(for Vcc) and switch off the ADD/SUB then switch off the
A0,A1,A2,A3 of Adder & switch on the B0 of 7486.
RESULTS :
By comparing the entries of theoretical values shown in truth table and practically (Virtual Lab.) observing
output LEDs, the logical operation of 4-bit binary parallel adder/subtractor have been verified.

1. What is virtual lab?

Answer01:
2. What opportunity is provided by virtual lab ?

Answer02:
3. What are the objectives of virtual labs?

Answer03:
4. List out some of the participating institutes of virtual labs?

Answer04:
5. What are the broad areas covered by virtual labs?

Answer05:

EXPT.No.12. VERIFY THE OPERATION OF 4- BIT SYNCHRONOUS/ ASYNCHRONOUS

COUNTER USING JK FLIP FLOP USING VIRTUAL LABS
AIM : To verify the truth table and timing diagram of 4-bit synchronous parallel counter and 4-bit asynchronous
parallel counter by using JK flip flop ICs and analyse the circuit of 4-bit synchronous parallel counter and 4-bit
asynchronous parallel counter with the help of LEDs display, using virtual labs.
REQUIREMENT FOR USE OF VIRTUAL LAB :
Sl. No. PARTICULARS REQUIRED

Windows7 or 10
1 Desktop Computer/Laptop
Operating System
2 Google Chrome Internet Browser -
3 www.vlab.co.in Web Site address
THEORY :
A counter is a device which stores (and sometimes displays) the number of times a particular event or
process has occurred, often in relationship to a clock signal. Counters are used in digital electronics for
counting purpose, they can count specific event happening in the circuit. For example, in UP counter a
counter increases count for every rising edge of clock.
1) Asynchronous Counter
In asynchronous counter we don’t use universal clock, only first flip flop is driven by main clock and the
clock input of rest of the following counters is driven by output of previous flip flops. Figure 01 shows the
circuit diagram of 4-bit asynchronous counter.
Figure01: 4-Bit Asynchronous Counter

Figure 02: Timing Diagram of 4-Bit Asynchronous Counter

It is evident from timing diagram as shown in figure 02, that Q0 is changing as soon as the trailing edge of
clock pulse is encountered, Q1 is changing when trailing edge of Q0 is encountered (because Q0 is like clock
pulse for second flip flop) and so on. In this way ripples are generated through Q0, Q1, Q2, Q3 hence it is
also called RIPPLE counter.
2) Synchronous Counter
Unlike the asynchronous counter, synchronous counter as shown in figure 03, has one global clock which
drives each flip flop so output changes in parallel. The one advantage of synchronous counter over
asynchronous counter is, it can operate on higher frequency than asynchronous counter as it does not
have cumulative delay because of same clock is given to each flip flop.
Figure03: 4-Bit Synchronous Counter

Figure 04: Timing Diagram of 4-Bit Synchronous Counter
From timing diagram as shown in figure 04, we see that Q0 bit gives response to each falling edge of clock
while Q1 is dependent on Q0, Q2 is dependent on Q1 and Q0 , Q3 is dependent on Q2,Q1 and Q0.
Truth Table of 4-bit Asynchronous/Synchronous Counter:
SL.No. CLOCK OUTPUTS

Q3 Q2 Q1 Q0
1 0 X X X X
2 1 0 0 0 0
3 2 0 0 0 1
4 3 0 0 1 0
5 4 0 0 1 1
6 5 0 1 0 0
7 6 0 1 0 1
8 7 0 1 1 0
9 8 0 1 1 1
10 9 1 0 0 0
11 10 1 0 0 1
12 11 1 0 1 0
13 12 1 0 1 1
14 13 1 1 0 0
15 14 1 1 0 1
16 15 1 1 1 0
17 16 1 1 1 1
18 17 0 0 0 0

STEPS FOR SELECTING EXPERIMENT FROM VIRTUAL LAB:
1. Open virtual lab website using google chrome/Mozilla web browser (www.vlab.co.in)
2. Select “ Electronics and Communication” area.
3. Select “ Digital Electronics Circuits Lab (IIT Kharagpur)” under area of “ Electronics and Communication”
area.
4. Click on “List of Experiments.”
5. Select the experiment “Design & verify of 4-bit Asynchronous/Synchronous counter using JK Flip Flop”.
6. Select Simulation.
PROCEDURE USING VIRTUAL LAB:
Step-1) Connect the supply(+5V) to the circuit.

Step-2) Press Counter button to start the counter and the data is simultaneously added to the Truth Table.
Step-3) Repeat step 2 and step 3 for another set of data.
Step-4) Then press "Generate Waveform" button to generate the timing diagram.
Step-5) Press the "Print " button after completing your simulation to get your results.
CIRCUIT DIAGRAMS OF VIRTUAL LAB:

1) 4-Bit Asynchronous Counter Using IC 7476

2) 4-Bit Synchronous Counter Using IC 7476
Dual JK Flip Flop IC

Synchronous UP/DOWN 4-bit Binary Counter IC

RESULT :
By comparing the entries of theoretical and practical (Virtual Lab.) output values shown in truth table, the
logical operation of 4-bit Asynchronous/Synchronous counters have been verified.
1. What do you mean by a counter?

Answer01:
2. Classify the counters.

Answer02:
3. What is an asynchronous counter?

Answer03:
4. What is modulus counter?

Answer04:
5. What is synchronous counter?

Answer05:
6. What is single mode counters?

Answer06:
7. What are multimode counters?

Answer07:
8. What are the applications of counters?

Answer08:
9. What is the maximum binary number counted by the counter?

Answer09:
10. What is the major drawback of a ripple counter?

Answer10:

CS304 Digital Systems Lab Manual Final

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CS304 Digital Systems Lab Manual Final

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DIGITAL SYSTEMS LABORATORY -1-

III Sem (CS)

INDORE INSTITUTE OF SCIENCE

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG.

INDORE INSTITUTE OF SCIENCE AND

This is to certify that Mr./Ms……………………………………………………………… with RGTU

Enrollment No. ..…………………………..has satisfactorily completed the course of experiments in

…………………….……………………………………………...………laboratory, as prescribed by Rajiv

Gandhi Proudhyogiki Vishwavidhyalaya, Bhopal for ……… Semester of the …………………….

Engineering Department during year 20….… − ....

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG.

DEPT.OF ELECTRONICS AND COMMN.

03. To prove De Morgan’s theorem.

04. To verify the operation of binary half adder and full

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG.

EXPT.No. 1. VERIFICATION OF TTL GATE OPERATION USING TRUTH TABLES

Sl. No. PARTICULARS RANGE / ID. No. QUANTITY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG.

Fig. (i) 2 INPUT AND Gate: Input A = Logic 0 or 1 Output , Y = (A . B)

The AND operation is represented by the operator “ . ” 1 1 1

Fig. (ii) 2 INPUT OR Gate: Output , Y = (A + B)

The OR operation is represented by the operator “ + ” 1 1 1

The NOT operation is represented by the operator “ ’ ”

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG.

Fig. (v) 2 INPUT NOR Gate: Output , Y = (A + B)’

Fig. (vi) 2 INPUT Ex-OR Gate: Output , Y = (A B)

The Ex-OR operation is represented by the operator “” 1 1 0

Fig. (vii) 2 INPUT Ex-NOR Gate : Output , Y = (AB)’ = (A B)

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG.

PIN DIAGRAMS OF TTL ICs :

VIVA QUESTIONS ANS ANSWERS:

1. What is the full form of TTL?

2. What is the IC number of HEX Inverter (NOT) gate?

3. What does the LS and HC stands for in the number of an IC?

6. List out the features of TTL ICs.

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG.

7. What is AND Gate?

9. What is NOT Gate?

10. What is the IC number of 2-input OR gate?

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG.

Sl. No. PARTICULARS RANGE / ID. No. QUANTITY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG.

CIRCUIT DIAGRAMS AND OBSERVATION TABLES:

Fig. (ii) Realization of AND Gate : Output , Y = (A .B)

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG.

NOR GATE AS UNIVERSAL GATE:

Fig. (vi) Realization of NOT Gate : Output, Y = (A)’

Fig. (vii) Realization of AND Gate : Output, Y = (A . B)

Fig. (viii) Realization of Ex-OR Gate :

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG.

PIN DIAGRAMS OF TTL ICs :

VIVA QUESTIONS AND ANSWERS:

1. Why NAND and NOR gates are called as universal gates?

2. What is the IC number of 2-input NAND gate IC?

3. What is the IC number of 2-input NOR gate IC?

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG.

EXPT.No.3. PROVE DE MORGAN’S THEOREM

AIM : To prove De Morgan’s theorem.

Sl. No. PARTICULARS RANGE / ID. No. QUANTITY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG.

CIRCUIT DIAGRAMS AND OBSERVATION TABLES:

Fig. (i) De Morgan’s I Theorem:

Output, Y1 = (A +B)’ Output, Y2 = (A’.B’)

Fig. (ii) De Morgan’s II Theorem :

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG.

Output, Y3 = (A.B)’ Output, Y4 = (A’+ B’)

PIN DIAGRAMS OF TTL ICs :

VIVA QUESTIONS AND ANSWERS:

1. State DeMorgan’s first theorem.

2. State DeMorgan’s second theorem.

3. What is the use of DeMorgan’s theorem?

4. State duality theorem.

5. What is the dual relation of Boolean relation A + 0 = A?

6. What is the dual relation of Boolean relation A + A’= 1?

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG.