ADE LAB UPDATED Manual-Draft 22 SCHEME - 23-24

DEPARTMENTOFELECTRONICS
&
COMMUNICATIONENGINEERING
IIISEMESTER LAB MANUAL
(2022 Scheme)
Analog and Digital System Design

Labboratory
BECL305
PreparedBy:
Mrs. Akshata Chavan, Assistant Professor, ECE
LabInstructor:
Mr. Srinivasa T, Technical Staff, ECE
Approved by
Dr. Praveen J
IQAC Director, Professor and Head, ECE
Analog & Digital System Design Laboratory (BECL305)
Vision and Mission of the Institute
Vision of the Institute

To develop technologically competent, humane and socially responsible
engineers and managers to meet the ever growing challenges of the
Global
Environment.
Mission of the Institute

• To provide quality technical and management education by applying
best
practices in teaching, learning and with the state of the art
infrastructuralfacilities.
• To mould engineers and managers with appropriate pedagogy to

develop
leadership qualities and skills by imbibing professional ethics to
make themindustry ready.
• To develop student-centric institution which evolves and fosters the

talents ofbudding engineers, managers and entrepreneurs and
prepare them to makeapositive contribution to the society.
• To promote Research and Consultancy through collaboration with

industriesand Government Organizations.
Department of ECE, GMIT, Davangere Page2

Vision, Mission, PEOs & PSOs of the Department
Vision of the Department

To excel in creating technically competent and socially responsible
Electronics
& Communication Engineers capable of contributing to the emerging
technology.
Mission of the Department

M1: Imparting effective technical education to excel in Electronics &
Communication Engineering.
M2: Adapting appropriate pedagogy to imbibe professionalism in
students.
M3: Inculcating Research culture and there by bridging the gap between
Academia and Industry.
Program Educational Objectives
PEO1: To deliver Engineering Skills and Knowledge by integrating basic

engineering concepts with core Electronics and Communication
Engineering to
solve the problems of the society.
PEO2: To exhibit technical competency by developing solutions in
diverse
areas of Electronics and Communication Engineering.
PEO3: To be receptive to emerging technologies and attain professional
competency through pursuing Research and life-long learning.
Program Specific Outcomes
PSO1: Design Analog and Digital Systems using emerging Technologies.
PSO2: Build different models by applying Technical knowledge

inCommunication, Networking, Signal Processing, VLSI and Embedded
Systems along with Programming and Simulation tools for a variety of
applications.

Program Outcomes
Graduates of Electronics & Communication Engineering by the time of

graduation will demonstrate:
PO1: Engineering knowledge: Apply the knowledge of mathematics, science,

engineering fundamentals, and an engineering specialization to the solution of
complex engineering problems.
PO2: Problem analysis: Identify, formulate, research literature, and analyze
complex engineering problems reaching substantiated conclusions using first
principles of mathematics, natural sciences, and engineering sciences.
PO3: Design/development of solutions: Design solutions for complex
engineering problems and design system components or processes that meet the
specified needs with appropriate consideration for the public health and safety,
and the cultural, societal, and environmental considerations.
PO4: Conduct investigations of complex problems: Use research-
based knowledge and research methods including design of experiments, analysis
and interpretation of data, and synthesis of the information to provide valid
conclusions.
PO5: Modern tool usage: Create, select, and apply appropriate techniques,
resources, and modern engineering and IT tools including prediction and
modeling to complex engineering activities with an understanding of the
limitations.
PO6: The engineer and society: Apply reasoning informed by the contextual
knowledge to assess societal, health, safety, legal and cultural issues and the
consequent responsibilities relevant to the professional engineering practice.
PO7: Environment and sustainability: Understand the impact of the
professional engineering solutions in societal and environmental contexts, and
demonstrate theknowledge of, and need for sustainable development.
PO8: Ethics: Apply ethical principles and commit to professional ethics and
responsibilities and norms of the engineering practice.
PO9: Individual and team work: Function effectively as an individual, and
as a member or leader in diverse teams, and in multidisciplinary settings.
PO10: Communication: Communicate effectively on complex engineering
activities with the engineering community and with society at large, such as,
being able to comprehend and write effective reports and design documentation,
make effective presentations, and give and receive clear instructions.
PO11: Project management and finance: Demonstrate knowledge and
understanding of the engineering and management principles and apply these to
one’s own work, as a member and leader in a team, to manage projects and in
multidisciplinary environments.
PO12: Life-long
Department of ECE, GMIT,learning:
DavangereRecognize the need for, and have the preparation
Page4
and ability to engage in independent and life-long learning in the broadest
context of technological change.
Analog and Digital Electronics Lab-21ECL35

III Semester
Course objectives:
•Understand the electronic circuit schematic and its working.
•Realize and test amplifier and oscillator circuits for the given specifications.
•Realize the opamp circuits for the applications such as DAC, implement
mathematicalfunctions and precision rectifiers.
•Study the static characteristics of SCR and test the RC triggering circuit.
•Design and test the combinational and sequential logic circuits for their
functionalities.
•Use the suitable ICs based on the specifications and functions.
Sl.No. List of Experiments

Design and set up the BJT common emitter voltage amplifier with and without
1 feedback and determine the gain-bandwidth product, input and output
impedances.
2 Design and set-up BJT/FET i) Colpitts Oscillator, ii) Crystal Oscillator
Design and set up the circuits using opamp: i)Adder, ii)Integrator,
3
iii) Differentiator and iv) Comparator.
Design 4-bit R-2R Op-Amp Digital to Analog Converter i) For a 4bit Binary input
4
using toggle switches ii) By generating digital inputs using mod-16
Design and implement(a) Half Adder & Full Adder using basic gates and NAND
5 gates,(b) Half subtractor & Full subtractor using NAND gates, (c) 4-variable
function using IC74151(8:1MUX).
Realize(i) Binary to Gray code conversion & vice-versa (IC74139),
6
(ii) BCD to Excess-3 code conversion and vice versa.
a)Realize using NAND Gates:i) Master-Slave JK Flip-Flop, ii) D Flip-Flop and iii)
7 T Flip-Flop b) Realize the shift registers using IC7474/7495:(i) SISO (ii) SIPO (iii)
PISO (iv) PIPO (v) Ring counter and (vi) Johnson counter.
Realizea) Design Mod – N Synchronous Up Counter & Down Counter using
8 7476 JK Flip-flopb) Mod-N Counter using IC7490 / 7476 c) Synchronous
counterusing IC74192.
Demonstration Experiments( For CIE)
Design and test the following using 555timer

9 i) Monostable Multivibrator
ii) AstableMultivibrator

Course outcomes (Course Skill Set):
C205.1: Design and analyze the BJT/FET amplifier and oscillator circuits.
C205.2: Design and test Opamp circuits to realize the mathematical computations,
DAC and Precision rectifiers.
C205.3: Design and test the combinational logic circuits for the given specifications.
C205.4: Test the sequential logic circuits for the given functionality.
C205.5: Demonstrate the basic electronic circuit experiments using SCR and 555
timer.
Program
Program Outcomes Specific
Course Outcomes
Outcomes
- CO
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO 1 PSO 2
C205.1 3 3 3 2 2 2 3 3
C205.2 3 3 3 2 2 2 3 3
C205.3 3 3 3 2 2 2 3 3
C205.4 3 3 3 2 2 2 3 3
C205.5 3 3 3 2 2 2 3 3
Average 3 3 3 2 2 2 3 3
C205 3 3 3 2 2 2 3 3
Assessment Details (both CIE and SEE)

The weightage of Continuous Internal Evaluation (CIE) is 50% and for Semester
End Exam (SEE) is50%. The minimum passing mark for the CIE is 40% of the
maximum marks (20 marks). A studentshall be deemed to have satisfied the
academic requirements and earned the credits allotted to eachcourse. The
student has to secure not less than 35% (18 Marks out of 50) in the semester-
endexamination (SEE).
Continuous Internal Evaluation (CIE):

CIE marks for the practical course is 50 Marks. The split-up of CIE marks for
record/ journal and test are in the ratio 60:40.
• Each experiment to be evaluated for conduction with observation sheet and

record write-up.Rubrics for the evaluation of the journal/write-up for
hardware/software experiments designedby the faculty who is handling the
laboratory session and is made known to students at thebeginning of the
practical session.
• Record should contain all the specified experiments in the syllabus and each

experiment write-upwill be evaluated for 10 marks.

• Total marks scored by the students are scaled downed to 30 marks (60% of
maximum marks).
• Weightage to be given for neatness and submission of record/write-up on
time.
• Department shall conduct 02 tests for 100 marks, the first test shall be
conducted after the 8thweek of the semester and the second test shall be
conducted after the 14th week of the semester.
• In each test, test write-up, conduction of experiment, acceptable result, and
procedural knowledgewill carry a weightage of 60% and the rest 40% for viva-
voce.
• The suitable rubrics can be designed to evaluate each student’s performance
and learning ability.Rubrics suggested in Annexure-II of Regulation book.
• The average of 02 tests is scaled down to 20 marks (40% of the maximum
marks).
The Sum of scaled-down marks scored in the report write-up/journal and
average marks of two tests isthe total CIE marks scored by the student.
Semester End Evaluation (SEE):
SEE marks for the practical course is 50 Marks.
SEE shall be conducted jointly by the two examiners of the same institute;
examiners are appointed bythe University.
All laboratory experiments are to be included for practical examination.
(Rubrics) Breakup of marks and the instructions printed on the cover page of
the answer script to bestrictly adhered to by the examiners. OR based on the
course requirement evaluation rubrics shall bedecided jointly by examiners.
Students can pick one question (experiment) from the questions lot prepared by
the internal /externalexaminers jointly.
Evaluation of test write-up/ conduction procedure and result/viva will be

conducted jointly byexaminers.
General rubrics suggested for SEE are mentioned here, writeup-20%,

Conduction procedure and resultin -60%, Viva-voce 20% of maximum marks.
SEE for practical shall be evaluated for 100 marks andscored marks shall be
scaled down to 50 marks (however, based on course type, rubrics shall
bedecided by the examiners).
Change of experiment is allowed only once and 15% Marks allotted to the
procedure part to be madezero.The duration of SEE is 03 hours Rubrics
suggested in Annexure-II of Regulation book.
Suggested Learning Resources:
1. Fundamentals of Electronic Devices and Circuits Lab Manual, David A Bell,
5th Edition, 2009, OxfordUniversity Press.

2. Op-Amps and Linear Integrated Circuits, Ramakant A Gayakwad, 4th
Edition, Pearson Education,2018. ISBN: 978-93-325-4991-3.
3. Fundamentals of Logic Design, Charles H Roth Jr., Larry L Kinney, Cengage
Learning, 7th Edition.
GENERAL INSTRUCTIONS
SAFETY:
➢ When students are doing experiment they have to be very care full.
➢ Students should have the prior knowledge about the lab they are doing.
➢ If any kind of wrong thing happened while doing the experiment. Students
have to
immediately switch off power supply on the work table.
ATTENDANCE:
1. Students have to come to the laboratory with proper dress code and ID Cards.
2. Students have to bring Observation note book, Record note book and calculators
etc..to the Laboratory.
3. Students have to show their observations with results after completion of their
experiments and they have to get is signed.
4. After completion of experiment students have to submit their completed
records to the faculty of their lab within a week.
DOING EXPERIMENTS:
1. Start the experiment as per the procedure.

2. Enter all readings in the tabulation.
3. Do not make any interconnections on the bread board when power is switched ON.
4. Take readings without any parallax error.
5. If any of the things are wrong, then switch off and modify the connections.
Informto the staff and then START.
CALCULATION:
1. Calculate all required quantities and enter in the tabulation.

2. Units are very, very important.
3. Draw the necessary graphs.
4. Write the result.
5. Show it to the staff for getting Signature.
RECORD:

1. As the name Implies, it is a record: permanent record for reference. Write neatly;
Draw circuit diagrams neatly and label correctly.
2. Enter readings in the tabulation.
3. Draw Graph. Complete the record before you come for next lab class.
4. Bring the record for submission during next lab class.
ADDITIONAL INSTRUCTIONS:
1. Before entering into the laboratory class, you must be well prepared for the
experiment that you are going to do on that day.
2. You must bring the related textbook, which may deal with the relevant
experiment.
3. Get the circuit diagram and block diagram without any wrong connections.
4. Get the reading verified. Then inform the technician so that supply to the
worktable
can be switched off.
5. You must get the observation note corrected within two days from the date of
completion of experiment.
6. If you miss any practical class due to unavoidable reasons, intimate the staff
incharge and do the missed experiment in the repetition class.
7. Such of those students who fail to put in a minimum of 75% attendance in the
laboratory class will run the risk of not being allowed for the University
Practical
Examination. They will have to repeat the lab course in subsequent semester
after
paying prescribed fee.
8. Acquire a good knowledge of the surrounding of your worktable. Know where
the
various live points are situated in your table.
9. In case of any unwanted things happening, immediately switch off the
mains in the worktable. The same must be done when there is a power
break during the experiment being carried out.

Experiment -1
Aim:Design and setup the BJT common emitter voltage amplifier using voltage
divider bias
with and without feedback and determine the gain-bandwidth product from its
frequency
response, input and output impedance.
Components Required:
Sl No Components Specification Quantity

1 Transistor BC107 1
47KΩ, 2.2KΩ,
2 Resistors 10KΩ, 820Ω and 1 each
680Ω
3 Capacitors 1 µF, 22µF 2,1
4 DC Supply - 1
5 CRO - 1
6 Bread Board - 1
7 CRO Probes - 2
8 Connecting Wires - 1 set
,
Theory:
RC-coupled CE amplifier is widely used in audio frequency applications in
radio
and TV receivers. It provides current, voltage and power gains. Base current controls
the
collector current of a common emitter amplifier. A small increase in base current
results
i n a relatively large increase in collector current. Similarly, a small decrease in base
currentcause large decrease in collector current. The emitter-base junction must be
forward biased
and the collector base junction must be reverse biased for the proper functioning of
an
amplifier. In the circuit diagram, an NPN transistor is connected as a common
emitter ac
amplifier. R1 and R2 are employed for the voltage divider bias of the transistor.
Voltage
divider bias provides good stabilization in dependent of the variations of β. The input
signal Vin is coupled through CC1 to the base and output voltage is coupled from

Collectror through the capacitor cc2.
The input impedance of the amplifier is expressed as Zin=R1||R2||(1+hFEre) and

outputimpedance as Zout = RC||RLwhere re is the internal emitter resistance of the
transistor
given by the expression=25mV/IE, where 25mV is temperature equivalent voltage at
room temperature.
Design:
Output requirements: Mid-band voltage gain of the amplifier = 50 and required
output
voltage swing=10V.
Selection of transistor
Select transistor BC107 since its minimum guaranteed hFE (=100) is more than the
required
gain (=50) of the amplifier.
Quick Reference data of BC107

Type: NPN-Silicon,
Application: In audio frequency
Maximum rating: VCB=50V,VCE=45V,VEB=6V,IC=100mA.
Nominal rating: VCE=5V, IC=2mA, hFE=100 to 500.
DC b i as i n g conditions VCC is taken as 20% more than required output swing.

Hence
VCC=12V.
IC=2mA, because hFE is guaranteed 100 at that current as per data sheet.
In order to make the operating point at the middle of the load line, assume the dc
conditions
VRC=40% of VCC = 4.8V,VRE=10% of VCC=1.2V and VCE=50% of VCC=6V.
Design of RC
VRC=IC×RC =4.8V.
From this, we get RC =2.4k, Use2.2k.

Design of RE
VRE=IE×RE=1.2V.
From this, we get RE=600Ω because IE≈IC, Use 680Ω std.
Design of voltage divider R1 and R2

Assume the current through R1 =10IB and that through R2 =9IB for a stable voltage
across R1 and R2 independent of the variations of the base current.
VR2 = Voltage drop across R2 =VBE+VRE.
i.e., VR2=VBE+VRE=0.6+1.2=1.8V. Also, VR2=9IBR2 =1.8V
But IB= IC/hFE = 2mA/100 = 20µA.
Then R = 1.8 / 9×20×10-6 = 10.6k, Use10k.
VR1=voltage across R1 =VCC-VR2=12V -1.8V =10.2V
Also, V = 10IR =10.1V.
Then R= 10.2/ (10×20×10-6) = 50k. Select 47k std.
Design of RL:
Gain of the common emitter amplifier is given by the expression
AV = - (rc/re). Where rc=RC||RL and re=25mV/IE=25mV/2mA=12.5Ω.
Since the required gain=50, substituting it in the expression we get, RL =845Ω, Use
820Ω
Design of coupling capacitors CC1 and CC2

XC1 should be less than the input impedance of the transistor. Here, Rin is the
series
impedance. Then XC1 ≤ = Rin/10. Here Rin = R1 || R2 || (1+hFEre) because RE
bypassed. We get Rin=1.1k.Then XC1≤110Ω. So, CC1≥1/2πfL×110=14µF.Use15µF
std. Similarly, XC2 ≤ Rout/10, where Rout = RC.Then XCE ≤ 240Ω. So, CC2 ≥
1/2π×240 = 6.6µF, Use10µF std.
Design of bypass capacitors CE

To bypass the lowest frequency (say100Hz), XCE should be less than or equal to the
resistance RE. i.e., XCE ≤ RE/10 Then, CE ≥ 1/(2π×100×68)=23µF.Use 22µF

Circuit Diagram:
i. CE Amplifier without feedback:
ii. CE Amplifier with feedback.

Procedure:
1. Test all the components using a multimeter. Setup the circuit and verify dc
bias conditions. To check dc bias conditions, remove input signal and
capacitors in the circuit.
2. Connect the capacitors in the circuit. Apply a100mVpeak to peak sinusoidal
signal fromthe function generator to the circuit input. Observe the input and
output waveforms onthe CRO screen simultaneously.
3. Keep the input voltage constant at100mV; vary the frequency of the input
signal from 0 to 1MHz or highest frequency available in the generator. Measure
the output amplitude
corresponding to different frequencies and enter it in tabular column.
4. Plot the frequency response characteristics on a graph sheet with gain in dB on
y-axis andlog f on x-axis. Mark log fL and log fH corresponding to 3dB points. (If
a semi-log graphsheet is used instead of ordinary graph sheet, mark f along x-
axis instead of log f).
5. Calculate the bandwidth of the amplifier using the expression BW= fH- fL.
6. Remove the emitter bypass capacitor CE from the circuit and repeat the steps
3 to 5 andobserve that the bandwidth increases and gain decreases in the
absence of CE.
Tabular Column: CE Amplifier without feedback

V in (P-P) = ……..


Experiment - 2
Aim:Design and set-up BJT/FET i) Colpitts Oscillator, ii) Crystal Oscillator and iii)
RC Phase shift oscillator
i) Colpitt’s Oscillator
To design and test the performance of BJT Colpitt’s Oscillators for the given
Frequency Fr.

47KΩ, 2.2KΩ, 10KΩ,
2 Resistors 820Ω 1 each
and 680Ω
3 Capacitors 0.01µf &1µf , 22 µf 2,1
4 DC Supply - 1
5 DCB - 2
6 DIB - 1
7 CRO - 1
8 Bread Board - 1
9 CRO Probes - 2
Theory:
A LC oscillator which uses two Capacitors and one Inductor in its feedback
network
is called Colpitt’soscillator. The common emitter amplifier provides a phase shift of
180°
hence feedback network has to provide another 1800 phase shift to satisfy the
condition of
positive feedback. As the centre of C1 and C2 is grounded, upper end becomes
positive and
lower end becomes negative and vice versa. So LC network introduces a phase shift
of 180°.
Design:

Output requirements: Mid-band voltage gain of the amplifier = 50 and required

output
voltage swing =10V.
Selection of transistor
Select transistor BC107 since its minimum guaranteed hFE(=100) is more than the
required
gain (=50) of the amplifier.
Quick Reference data of BC107
Type: NPN-Silicon, Application: In audio frequency Maximum rating: VCB=50V,

VCE=45V,VEB= 6V,IC = 100mA. Nominal rating: VCE=5V, IC =2mA, hFE=100 to 500.
DC biasing conditions VCC is taken as 20% more than required output swing. Hence
VCC=12V. IC=2mA, because hFE is guaranteed 100 at that current as per data
sheet.
In order to make the operating point at the middle of the load line, assume the dc
conditions
VRC = 40% of VCC=4.8V,VRE=10% of VCC=1.2V and VCE=50% of VCC=6V.
Design of RC
VRC=IC×RC=4.8V.From this, we get RC=2.4k.Use2.2k.
Design of RE
VRE=IE×RE=1.2V.
From this, we get RE= 600Ω because IE≈IC.Use680Ωstd.
Design of voltage divider R1 and R2

Assume the current through R1=10IB and that through R2=9IBfor a stable voltage
across R1
and R2 independent of the variations of the base current.
VR2=Voltage drop across R2=VBE+VRE.
i.e.,VR2=VBE+VRE=0.6+1.2=1.8V.
Also,VR2= 9IBR2=1.8V
IB = IC / hFE = 2mA/100 = 20µA
R2 = VR2/ 9IB = 1.8/(9*20*10-6) = 10K

Design of RL:
Gain of the common emitter amplifier is given by the expression
AV = - (rc / re). Where rc = RC||RL and re=25mV/IE = 25mV/2mA=12.5Ω.
Since the required gain=50, substituting it in the expression we get, RL =845Ω. Use
820Ω
std.
Design of coupling capacitors CC1 and CC2

XC1 should be less than the input impedance of the transistor. Here, Rin is the series
impedance.
Then XC1≤=Rin/10. Here Rin=R1||R2||(1+hFEre) because is RE bypassed.
We get Rin =1.1k.Then XC1≤110Ω. So, CC1≥1/2πfL×110=14µF.Use15µFstd.
Similarly, XC2≤Rout/10, where Rout= RC.Then XCE ≤ 240Ω.
So, CC2 ≥ 1/2π×240 = 6.6µF. Use10µF std.
Design of bypass capacitors CE

To bypass the lowest frequency (say100Hz), XCE should be less than or equal to
theresistance RE.
i.e., XCE≤RE/10 Then, CE ≥ 1/(2π×100×68)=23µF.Use 22µF
Design of tank circuit:

Given: Frequency Fr= , Assume L= 100µH &Ceq= C1C2/(C1+C2)
Circuit Diagram for Colpitts Oscillator:

RB1=47KΩ, Rc= 2.2KΩ, RB2= 10KΩ, RE= 680Ω, CE= 22µF, Ci=C0= 1µF, L= 200mH,
C1 = C2 = 0.01µf
Procedure:
1. Assuming L=100µH and frequency f=225 KHz calculate the value of capacitance
C1
and C2.
2. Connections are made as shown in the circuit diagram.
3. Observe the waveform on the CRO and note down the time period.
4. Calculate the frequency.
5. Compare the frequency of step 1 and step 4.
Tabular Column:
ii) Crystal Oscillator

Design and set-up the crystal oscillator and determine the frequency of oscillation.
Sl. No Components Specification Quantity
47KΩ, 2.2KΩ, 10KΩ,
2 Resistors 820Ω 1 each
and 680Ω
3 Capacitors 1µf , 22 µf 1 each
4 DC Supply - 1
6 Crystal 4 MHz 1
7 CRO - 1
8 Bread Board - 1
9 CRO Probes - 2

Theory:
The crystals are either naturally occurring or synthetically manufactured,
exhibiting
the piezoelectric effect. The piezoelectric effect means under the influence of the
mechanical
pressure, the voltage gets generated across the opposite faces of the crystal. If the
mechanical
force is applied in such a way to force the crystal to vibrate, the AC voltage gets
generated
across it.Conversely, if the crystal is subjected to AC voltage, it vibrates causing
mechanical
distortion in the crystal shape. Every crystal has its own resonating frequency
depending on
its cut. So under the influence of the mechanical vibrations, the crystal generates an
electricalsignal of very constant frequency. The crystal has a greater stability in
holding the constantfrequency in order of mega Hz. A crystal oscillator is basically a
tuned oscillator using apiezoelectric crystal as its resonant tank circuit. The crystal
oscillators are preferred whengreater frequency stability is required. Hence the
crystals are used in watches,
communication transmitters and receivers etc.
Design: Design of amplifier part is similar to colpitts oscillator
Circuit Diagram:

RB1=47KΩ, Rc= 2.2KΩ, RB2= 10KΩ, RE= 680Ω, CE= 22µF, C0= 1µF, Crystal (4MHz)
Procedure:

2. Note down the frequency from the crystal.
3. Observe the waveform on the CRO and note down the time period.
4. Calculate the frequency.
5. Compare the frequency of step 2 and step 4.
Nature of Graph:

iii) RC – Phase Shift Oscillator
Aim: To find the frequency of oscillations of the RC phase Shift oscillator and to
measure the
phase shift of each Section of the RC network.
47KΩ 2
33KΩ 1
2 Resistors 2.2KΩ 1
8.2KΩ 1
2.7KΩ 1
0.01µf 3
3 Capacitors
47 µf 1
4 DC Supply - 1
5 Potentiometer 10KΩ - 1
6 CRO - 1
7 Bread Board - 1
8 CRO Probes - 2
Circuit Diagram:

Theory:
A phase shift oscillator can be defined as; it is one kind of linear oscillator
which is used to generate a sine wave output. It comprises of an inverting amplifier
component like operational amplifier otherwise a transistor. The output of this
amplifier can be given as input with the help of the phase shifting network. This
network can be built with resistors as well as capacitors in the form of a ladder
network. The phase of the amplifier can be shifted to 1800 at the oscillation
frequency by using a feedback network to provide a positive response. These types of
oscillators are frequently used as audio oscillators on audio frequency. This article
discusses an overview of RC phase shift oscillator.
RC phase-shift oscillator circuit can be built with a resistor as well as a capacitor.

This circuit offers the required phase shift with the feedback signal. They have
outstanding frequency strength and can give a clean sine wave for an extensive range
of loads. Preferably an easy RC network can be expected to include an o/p which
directs the input with 90o.
Design:
On applying KVL to output loop, we get
𝑽𝒄𝒄 = 𝑰𝒄𝑹𝒄 + 𝑽𝒄𝒆 + 𝑰𝒆𝑹𝒆
Where, 𝑽𝒆 = 𝑰𝒆𝑹𝒆
Find Rc
SinceIb is very small when compare with Ic,
𝑰𝒄 ≅ 𝑰𝒆
𝑽𝒆
𝑹𝒆 =
𝑰𝒆
𝑽𝒃 = 𝑽𝒃𝒆 + 𝑽𝒆
𝑽𝒄𝒄𝑹𝒃𝟐
𝑽𝒃 =
𝑹𝒃𝟏 + 𝑹𝒃𝟐
𝑹𝒃
𝑺=𝟏+
𝑹𝒆
Find Rb,
𝑹𝒃 = 𝑹𝒃𝟏||𝑹𝒃𝟐
Find Rb1 & Rb2,

Coupling and Bypass capacitors can be found out by,
Input coupling capacitor is given by,
|𝑹𝒃}
𝑿𝒄𝒊 = {[𝒉𝒌 + (𝟏 + 𝒉𝒌)𝑹𝒆]|
𝟏𝟎
Find Ci,
𝟏
𝑿𝒄𝒊 =
𝟐𝝅𝒇𝑪𝒊
Find C0,
𝟏
𝑿𝒄𝟎 =
𝟐𝝅𝒇𝑪𝟎
𝑹𝒆
Bypass Capacitor is given by, 𝑿𝒄𝒆 = 𝟏𝟎
Find Ce,
𝟏
𝑿𝒆 =
𝟐𝝅𝒇𝑪𝒆
Procedure:
1. Connections are made as per the circuit diagram.

2. Set the value of Rc (4KΩ – 8KΩ) by varying DRB and observe the output
waveform at ‘0’ on CRO which is sinusoidal.
3. Now, the CRO probe is changed to position ‘B’ such that the output
Waveform at B is observed on CRO which is shifted by 60o w.r.t ‘0’.
4. The output waveform at ‘C’ is observed on CRO, which is shifted by
120 o w.r.t ‘0’.
5. The output waveform at ‘D’ is observed on CRO, which is shifted by 180o w.r.t
‘0’.
6. Theoretically the frequency of oscillations is calculated by the formula,
f=1/2‫ח‬RC√6+4K, K=RC/R
7. Practically the time period ‘T’ on CRO is noted and frequency f = 1/T iscalculated.
8. The readings for different values of RC at 4K,5K,6K,7K and 8K are noted
And are tabulated as shown in the tabular form for different Lissajous
pattern.
9. A graph is plotted for phase and amplitude locating the phase shift
observed On CRO at different positions of (B,C,D)


Result:

Experiment - 3
Aim:To design Adder, Integrator, Differentiator and Comparator using Op-Amp.
Sl. No Equipment/Component Range Quantity
1 IC 741 1 1
1kΩ, 1.5 KΩ, 10 KΩ,
2 Resistor 3, 2, 1, 1, 2
15KΩ, 100 Ω,
0.1µF, 0.01 µF, 0.005
3 Capacitors 1, 1, 1
µF
4 Regulated Power supply (0 – 30V),1A 1
5 Function Generator - 1
6 Cathode Ray Oscilloscope - 1
7 Multimeter - 1
Theory:
An adder is an electronic circuit that produces an output, which is equal to the sum
of the
applied inputs. This section discusses about the op-amp based adder circuit. An op-
amp
based adder produces an output equal to the sum of the input voltages applied at its
invertingterminal. It is also called as a summing amplifier, since the output is an
amplified one.According to the virtual short concept, the voltage at the inverting
input terminal of an opamp is same as that of the voltage at its non-inverting input
terminal. So, the voltage at the
inverting input terminal of the op-amp will be zero volts.

An Integrator is an electronic circuit that produces an output that is the integration

of the
applied input. This section discusses about the op-amp based integrator. An op-amp
based
integrator produces an output, which is an integral of the input voltage applied to its
invertingterminal. According to virtual short concept, the voltage at the inverting
input terminal of opamp will be equal to the voltage present at its non-inverting input
terminal. So, the voltage at the inverting input terminal of op-amp will be zero
volts.The nodal equation at the inverting input terminal is

Integrating both sides of the equation shown above, we get
So, the op-amp based integrator circuit will produce an output, which is the integral
of input
voltage Vi, when the magnitude of impedances of resistor and capacitor are reciprocal
to
each other.TheDifferentiator circuit performs the mathematical operation of
differentiation;
That is, the output waveform is the derivative of the input waveform. The
differentiator may beconstructed from a basic inverting amplifier if an input resistor
R1 is replaced by a capacitorC1. The expression for the output voltage is given as,
Vo = - RfC1 ( dVi /dt )
Here the negative sign indicates that the output voltage is 180 0 out of phase with the
input
signal. A resistor Rcomp= Rfis normally connected to the non-inverting input terminal
of the
op-amp to compensate for the input bias current. A workable differentiator can be
designed
by implementing the following steps:
1. Select faequal to the highest frequency of the input signal to be differentiated.

Then,
assuming a value of C1 < 1 μF, calculate the value of R f.
2. Choose fb= 20 faand calculate the values of R1 and Cfso that R1C1 = RfCf.

The differentiator is most commonly used in wave shaping circuits to detect high
frequency components in an input signal and also as a rate–of–change detector in FM
modulators.
A Comparator is a circuit which compares a signal voltage applied at one input of an

opamp with a known reference voltage at the other input. It is basic all an open loop
op-amp with output ±Vsat as in the ideal transfer characteristics.
It is clear that the change in the output state takes place with an increment in input
Vi of only 2mv.This is the uncertainty region where output cannot be directly defined.
There are basically 2 types of comparators.
1. Non inverting comparator

2. Inverting comparator.
The applications of comparator are zero crossing detectors, window detector, time
marker generator and phase meter.
1. Adder:
Circuit Diagram:
Applying KCL to node A,
------ (1)
From the concept of virtual ground at node A, VA = 0 hence,
Say if R1 = R2 then,

------- (2)
Procedure for Adder:

1. Circuit is rigged up as shown in Figure 1.
2. Circuit is energized using ±12 V supply.
3. Two different signals V1, V2 (DC) are applied to the inputs.
4. For different values of input voltages and corresponding outputs are
tabulated.
Tabulation:
Sl No V1 volts V2 volts Vo volts
1 2.5 2.5 -5
2
3
Calculations:
Case1:
Vo = - (V1 + V2)
If V1 = 2.5V and V2 = 2.5V, then
Vo= - (2.5 + 2.5) = - 5V.
2. Integrator:
Circuit Diagram:

Design of integrator to integrate at cut-off frequency 1 KHz:

Tabulation:
Take Vin = 2 Vp-p
Input Square Wave Output Spike
Amplitude Vp-p Time Period Amplitude Vp-p
Time Period ms
Volts ms Volts
Input Sine wave Output Cosine

Amplitude Vp-p Amplitude Vp-p
Time Period ms Time Period ms
Volts Volts

Calculations:
Procedures for Integrator Circuit:

1. For the given frequencies fa and fb, values of Rf, Cf, R1 are calculated as per
the
design.
2. Circuit is rigged up as shown in figure 2 and energized.
3. Sinusoidal/square waves are applied to the input and output is observed.
4. Amplitude and time period of the output wave form are tabulated.

3. Differentiator:
Circuit Diagram:
Design:
Design a differentiator to differentiate an input signal with a cutoff frequency of
1KHz.
Apply a sine wave & square wave of 2Vp-p and 1KHz frequency, observe the output.

Select load resistance RL = 10 kΩ


Procedures for Integrator Circuit:

1. For the given frequencies faand fb, values of R1, Rf, C1, Cf, are calculated as per
the
design.
2. Circuit is rigged up as shown in figure 4 and energized.
3. Sinusoidal/square waves are applied to the input and output is observed.
4. Amplitude and time period of the output wave form are tabulated.

4. Comparator
Circuit Diagram
Procedure:
1.Connections are made as per the circuit diagram.
2.Select the sine wave of10V peak topeak ,1K Hz frequency.
3.Apply the reference voltage 2V and trace the input and output wave forms.
4.Superimpose inputand output waveforms and measure sine wave amplitude
withreferencetoVref.
5.Repeatsteps3and 4with referencevoltagesas2V,4V,-2V,-4Vandobserve the
waveforms.
6.Replace sine wave input with 5V dc voltage and Vref=0V.
7.Observe dc voltage atoutput using CRO.
8.Slowly increase Vrefvoltage and observe the change in saturation voltage.
Result:Adder, Integrator, Differentiator and Comparator are designed using op-amp

IC-741 and theirperformance is successfully tested.

Experiment-4
Aim: To design the 4-Bit R – 2R Opamp Digital To Analog Converter i)Using 4 Bit
Binary Input From Toggle Switchesand ii)By Generating Digital Inputs Using Mod-
16Counter.
SL COMPONENT QUANTITY
NO.
1 Op-amp 741 1
2 Resistors -7.5K 3
Resistors -15K 6
3 Power supply 1
4 Digital multi- 1
meter
5 Connecting 1 set
wires.
Theory:
i) Using 4 Bit Binary Input From Toggle Switches
A 4-bit DAC using R-2R ladder network and an Op-amp voltage follower acting as
a buffer stage is shown in Fig 1. D0, D1, D2 and D3 are the digital inputs. Each
digital input may be low (0) or high(1).VR (0) = 0 and VR (1) = VR = 5V. (Reference
voltage can be selected depending on maximum Analog o/p voltage required. If the
digital inputs are obtained from a Digital IC trainer, then VR = + 5 V = constant /
DC referencevoltage).The analog output voltage VO for a 4-bit DAC shown in Fig 1
can be written as below:
Output VO = (23 D3 + 22 D2 + 21 D1 + 2o Do) V
ii) By Generating Digital Inputs Using Mod-16Counter
In the circuit given above, a counter is connected in place of the toggle

switches. Introduce a clock signal (symmetrical square wave pulse) from the
signal generator and see the output waveform ona DSO and save. Reproduce
the same in your recordbook.

Procedure:
1. Make connections as shown in circuitdiagram.
2. For different digital inputs, measure the output voltage using a digitalmulti-
meter.
3. Enter the readings in the truth table and verify with theoretical values listed
in thetable.
4. Draw the Staircase graph as depictedbelow
Circuit Diagram:

Analog & Digital Electronics Lab (21ECL35)
Example Calculations:
When upper three digital inputs are set to 0 that is D3 = D2 = D1 = 0
(low state) and Do= 1 (High state) and VR = +5 Volts.
For a 4-Bit DAC using
R-2Rladder network, The Resolution = V = VR / 24= 0.208333 Volts
V = 0.208333Volts represents the “Smallest change in O/P voltage”
or“step size” or “Resolution” for the R-2R ladder network.
When all the Digital inputs are set to one (High state) that is
D3=D2=D1=Do=1(high state), then VO(max) = 15×VR/24 = 3.125VoltsOther
calculations are left as exercise to the students
By generating digital inputsusing mod-16 counter Specimen

Graph:
The Staircase Output

Result:

Experiment-5
Aim: Realization of half/full adder and half/full subtractor using basic
logic gates and 4 variable functions using IC74151.
Sl.No. Components Required Quantity
1 ICs : EX-OR-7486 01
2 IC: 74151 01
3 AND-7408 02
4 OR-7432 01
5 NAND-7400 03
6 NOT – 7404 01
7 Trainer Kit 01
8 Patch cards ----
1. Half Adder
Theory
A combinational logic circuit that performs the addition of two
data bits, A and B, is called a half-adder. Addition will result in
two output bits; one of which is the sum bit, S, and the other is
the carry bit, Cout.
K-Mapfor Half Adder

Boolean Expression
SUM (S) = A B` + A` B
= AB
Cout= A.B
Realization of Half Adder using basic gates:
Realization of half adder using NAND gates:

Procedure:
1. Read the theory and understand the operation of the logic circuit.
2. Insert the ICs required for the respective logic circuits onto the IC
base. Ensure that the DC trainer kit is in OFF condition while
inserting and removing the IC.
3. Verify the individual functionality of the gates before making the
connections.
4. Make the connections as per the logic circuit.
5. Verify the logic circuits with respect to the Truth Table and observe
the outputs.
6. Write the conclusion of the experiment.
2. Full adder
Theory
The half-adder does not take the carry bit from its previous stage into
account. This carry bit from its previous stage is called carry-in bit. A
combinational logic circuit that adds two data bits, A and B, and a carry-in
bit, Cin, is called a full-adder.

K-map for full adder
Realization of full adder using logic gates:

Boolean expression for the realization of full adder using two

half adders:

Realization of full adder using NAND gates:

3. Half subtractor
Theory
Subtracting a single-bit binary value B from another A (i.e. A -B)
produces a difference bit D and a borrow out bit B-out. This operation is
called half subtraction and the circuit to realize it is called a half subtractor.
K-map for half subtractor
Boolean expression for half subtractor:

Realization of half subtractor using logic gates:
Realization of half subtractor using basic gates

Realization of half subtractor using NAND gates:
4. Full subtractor
Theory
• The Full subtractor is a combinational circuit which is used to

perform subtraction of three bits.
• It has three inputs, A (minuend) and B (subtrahend) and C
(subtrahend)
• It has two outputs D (difference) and Br (borrow).

K-map for full subtractor
Realization of full subtractor using logic gates:
𝐃 = 𝐀⊕𝐁⊕𝐂
𝐁ORROW = 𝐀′ 𝐁 + 𝐀′ 𝐂 + 𝐁𝐂

Realization of full subtractor using two half subtractors:

Realization of full subtractor using NAND gates
4 -variable function using IC74151 (8:1MUX).
Multiplexer IC – 74151 (8 TO 1 Multiplexer)

• The 74151 is an 8 to 1 Multiplexer / Data Selector.
• It provides two outputs. One is active HIGH, the other is active LOW.

PIN Configuration
Full adder using IC 74151:

It performs the addition of 3 inputs and produces two outputs sum and
carry.

Full subtractor using IC74151:
It performs the subtraction of 3 inputs and produces two outputs difference

and borrow.

Realize the following Boolean function using IC74151:

Procedure:
1. Place the ICs on the IC trainer Kit.

2. Connect VCC and Ground to respective pins of IC Trainer Kit.
3. Make circuit connections as per the circuit diagram.
4. Connect the inputs to the input switches provided in the IC Trainer Kit.
5. Connect the output to the output switches of output LEDs.
6. Verify for all the combinations of input according to the truth table.
Result:

Experiment-6
Aim: Realization of Binary to Gray code conversion & vice-versa

and BCD toExcess-3 code conversion and vice versa.
Components required:
i) Binary to gray code conversion (74139)
Theory:
The Binary to Gray code converter is a logical circuit that is used to convert
the binary code into its equivalent Gray code. By putting the MSB of 1 below
the axis and the MSB of 1 above the axis and reflecting the (n-1) bit code
about an axis after 2n-1 rows, we can obtain the n-bit gray code.

Truth TableCircuit Diagram
ii) Gray code to Binary conversion (74139)

The Most Significant Bit (MSB) of the binary code is always equal to
the MSB of the given gray code.Other bits of the output binary code can
be obtained by checking the gray code bit at that index. If the current
gray code bit is 0, then copy the previous binary code bit, else copy the
invert of the previous binary code bit.
b2=g2, b1=g1⊕g2, and b0=g0⊕g1⊕g2.

Truth TableCircuit Diagram
iii) Excess-3 to BCD Code conversion using IC-7483
Theory:
Excess-3 code to BCD system is formed by subtracting 0011 from each
Excess-3 valuewhilethe BCD to Excess-3 system is formed by adding 0011
to each BCD value. As it is clear by the name, a BCD digit can be converted
to its corresponding Excess-3 code by simply adding 3 to it.The excess-3
code (or XS3) is a non-weighted code used to express code used to express
decimal numbers. It is a self-complementary binary coded decimal (BCD)
code and numerical system which has biased representation.

Excess-3 to BCD code conversion using IC-7483
BCD to Excess-3 code conversion using IC-7483
Excess-3 to BCD Code Conversion Truth Table

BCD to Excess-3 Code Conversion Truth Table:
Procedure:
1. Read the theory and understand the operation of the logic circuit.
2. Write the theoretical output for each truth table.
3. Insert the ICs required for the respective logic circuits onto the IC
base. Ensure that the DC trainer kit is in OFF condition while
inserting and removing the IC.
4. Verify the individual functionality of the gates before making the
connections if required.
5. Make the connections as per the logic circuit.
6. Apply minuend and subtrahend bits on A and B.
7. Verify the logic circuits with respect to the Truth Table and observe
the outputs.
8. Write the conclusion of the experiment.
Result:

Experiment- 7
Aim: a)Realize using NAND gates i) Master-Slave JK Flip-Flop ii) D Flip-
Flop iii) T Flip-Flop
Truth Table Verification Of Flip Flops
i)Master-Slave JKFlip-Flops
ii)DFlip-Flops
iii)TFlip-Flops
SL. NO. Component Quantity

1 IC7400 2
2 IC7410 1
3 Patch cords 1 set
4 IC trainer Kit 1
Theory:
A flip-flop is a binary storage device which can store either logic 0 or 1.
i)Master Slave JK flip-flop: The Master-Slave Flip-Flop is basically a

combination of two flip-flops- one JK flip-flop and other SR flip flop which
are connected together in a series configuration. Out of these, one acts as
the“master”and the other as a“slave”. The output from the master flip flop
is connected to the two inputs of the slave flip flop whose output is fed back
to inputs of the master flip flop.In addition to these two flip-flops, the circuit
also includes an inverter. The inverter is connected to clock pulse in such a
way that the inverted clock pulse is given to the slave flip-flop. In other
words if CP=0 for a master flip-flop, then CP=1 for a slave flip-flop and if
CP=1 for master flip flop then it becomes 0 for slave flip flop.
When the clock pulse goes to 1, the slave is isolated; J and K inputs may
affect the state of the system. The slave flip-flop is isolated until the CP goes
to 0. When the CP goes back to 0, information is passed from the master
flip-flop to the slave and output is obtained.Firstly the master flip flop is
positive level triggered and the slave flip flop is negative level triggered, so
the master responds before the slave.
ii) Clocked D flip flop: The D flip-flop is a clocked flip-flop with a single

digital input ‘D’. Each time a D flip-flop is clocked, its output follows the
state of ‘D’. The D Flip Flop has only two inputs D and CP. The D inputs go
precisely to the S input and its complement is used to the R input.
iii) Clocked T flip flop: T flip flop is a single input flip flop. Along with this
input, we need to give a clock signal to the flip flop. The T flip flop only
works when a clock signal is high. When the T signal is set low (0), it will not
affect the present state of the output and the response will not change
Procedure:
1. Insert the appropriate IC into the IC base or Zif socket
2. Make connections as shown in the circuit diagram.
3.Provide the input data via the input switches or toggle switches and
observe the output on output LEDs
4. Verify the operation using the truth table
i) Realization of Master Slave JK Flip-Flop
Block Diagram:
Truth Table:

Logic Diagram:
ii)Realizationof Clocked D Type Flip-Flop

Truth Table:
Symbol Logic Diagram

iv) Realization Of Clocked T Flip-Flop
Truth Table
LogicSymbol Logic Diagram

Aim: To realize the SISO, SIPO, PIPO, PISO, Ring counter and Johnson
counter using IC-7495.
SL COMPONENT QUANTITY
NO.
1 IC7495 1
2 IC7404 1
3 Patch cords 1 set
4 IC trainer Kit 1
Theory:
The IC7495 is a 4-Bit Shift Register with serial and parallel
synchronous operating modes. It has a Serial (DS) and four Parallel (P0–P3)
Data inputs and four Parallel Data outputs (Q0–Q3). The serial or parallel
mode of operation is controlled by a Mode Control input (S) and two Clock
Inputs (CP1) and (CP2). The serial (right-shift) or parallel data transfers
occur synchronous with the HIGH to LOW transition of the selected clock
input. When the Mode Control input (S) is HIGH, CP2 is enabled. A HIGH to
LOW transition on enabled CP2 transfers parallel data from the P0–P3
inputs to the Q0–Q3 outputs. When the Mode Control input (S) is LOW, CP1
is enabled. A HIGH to LOW transition on enabled CP1 transfers the data
from Serial input (DS) to Q0 and shifts the data in Q0 to Q1, Q1 to Q2, and
Q2 to Q3 respectively (right-shift). A left-shift is accomplished by externally
connecting Q3 to P2, Q2 to P1, and Q1 to P0, and operating the LS95B in
the parallel mode (S = HIGH) .Shift Registers are sequential logic circuits,
capable of storage and transfer of data.
1)Serial-in to Parallel-out (SIPO)-the register is loaded with serial data, one

bit at a time, with the stored data being available at the output in parallel
form.
2)Serial-in to Serial-out (SISO)-the data is shifted serially “IN” and “OUT” of
the register, one bit at a time in either a left or right direction under clock
control.
3)Parallel-in to Serial-out (PISO)-the parallel data is loaded into the register
simultaneously and is shifted out of the register serially one bit at a time
under clock control.
4)Parallel-in to parallel-out (PIPO)-the parallel data is loaded simultaneously
into the register, and transferred together to their respective outputs by the

same clock pulse.

5)Ring counter is a sequential logic circuit that is constructed using shift
register. Same data re-circulates in the counter depending on the clock
pulse.That means if the output of the first flip flop is 1, then this is
transferred to its next stage i.e. 2nd flip flop. By transferring the output to
its next stage, the output of first flip flop becomes 0. And this process
continues for all the stages of a ring counter. If we use n flip flops in the ring
counter, the ‘1’ is circulated for every n clock cycles.
6)The Johnson counter is a modification of ring counter. In this the inverted
output of the last stage flip flop is connected to the input of first flip flop. If
we use n flip flops to design the Johnson counter, it is known as 2n bit
Johnson counter or Mod 2n Johnson counter.This is an advantage of the
Johnson counter that it requires only half number of flip flops that of a ring
counter uses, to design the same Mod.
i) SISO
Logic DiagramTruth Table
Cloc Seriali/ QA QB QC QD
k p
1 do=0 0 X X X
2 d1=1 1 0 X X
3 d2=1 1 1 0 X
4 d3=1 1 1 1 0=do
5 X X 1 1 1=d1
6 X X X 1 1=d2
7 X X X X 1=d3

ii) SIPO ( Right shift)

Cloc Seriali/ QA QB QC QD
k p
1 0 0 X X X
2 1 1 0 X X
3 1 1 1 0 X
4 1 1 1 1 0
iii) PISO
Clk Paralleli/p Parallelo/p
Logic DiagramTruth Table A B C D QA QB QC QD
1 1 0 1 1 1 0 1 1
Parallel I /p Parallelo/p
Mode Clk
A B C D QA QB QC QD
1 1 1 0 1 1 1 0 1 1
0 2 X X X X X 1 0 1
0 3 X X X X X X 1 0
0 4 X X X X X X X 1
iv) PIPO
Logic Diagram Truth Table

v) RING Counter
Logic Diagram Truth Table
Mode ClockClock
Mode QA QB
QA QC
QB QDQC QD
1 1 1 11 01 00 0 0 0
0 0 2 21 10 01 0 0 0
0 0 3 31 10 10 0 1 0
0 0 4 41 10 10 1 0 1
0 0 5 50 11 10 1 0 0
0 0 6 60 0 1Repeats
1
0 7 0 0 0 1
0 8 0 0 0 0
0 9 1 0 0 0
vi) JOHNSON Counter
0 10 Repeats
Result:

Experiment- 8
Aim: To design Mod – N synchronous Up counter & Down counter
using 7476 JK flip- flop
SL NO. COMPONENT QUANTITY

1 IC7476 2
2 IC7408 1
3 Patch cords 1 set
4 IC trainer Kit 1
Theory:
The 74LS76 offers individual J, K, Clock Pulse, Direct Set and Direct Clear
inputs. These dual flip-flops are designed so that when the clock goes
HIGH, the inputs are enabled and data will be accepted. The Logic Level of
the J and K inputs will perform according to the Truth Table as long as
minimum set-up times are observed. Input data is transferred to the
outputs on the HIGH-to-LOW clock transitions.Synchronous Counters are
so called because the clock input of all the individual flip-flops within the
counter are all clocked together at the same time by the same clock signalA
mod-8 counter stores a integer value, and increments that value (say) on
each clock tick, and wraps around to 0 if the previous stored value was 7
Procedure:
1. Insert the appropriate IC into the IC base or Zip socket.
2. Make connections as shown in the circuit diagram.
3.Provide the input data via the input switches or toggle switches and
observe the output on output LEDs.
4. Verify the operation using the truth table.
.

Pin Diagram of IC-7476Function Table
Transition Table
Design for Mod 8 Up- Counter

K- Map
Circuit Diagram of Mod - 8 Up -Counter

Aim: To realize mod-n counter using IC-7490

1 IC7490 2
2 IC7408 1
3 IC7411 1
4 Patch cords 1 set
5 IC trainer Kit 1
Theory:
TheIC-7490 isa decade counter. It contains four master slave flip flops
It is a simple counter, i.e. it can count from 0 to 9 cyclically in its natural
mode. It counts the input pulses and the output is received as a 4-bit binary
number through pins QA, QB, QC and QD.
The binary output is reset to 0000 at every tenth pulse and count
starts from 0 again. A pulse is also generated (probably at pin 9) as it resets
its output to 0000. The chip can count up to other maximum numbers and
return to zero by changing the modes of 7490. These modes are set by
changing the connection of reset pins R1- R2 and S1-S2.
For example, if either R1& R2 are high or S1& S2 are ground, then it will
reset QA, QB, QCand QD to 0. If resets S1& S2 are high, then the count on
QA, QB, QC and QD goes to 1001.
7490 has an inbuilt divide by two and divide by five counters which
can be connected in different fashion by changing the connections. It can be
used as a divide by 10 counters by connecting QA with (clock) input2,
grounding all the reset pins, and giving pulse at (clock) input1.
The other high counts can be generated by connecting two or more
7490 ICs. For example, if two 7490 are connected in a manner that input of
one becomes the output of other, the second IC will receive a pulse on every
tenth count and will reset at every hundredth count. Thus this system can
count from 0 to 99 and give corresponding BCD outputs.

Pin Configuration ofIC-7490 Block Diagram of IC-7490
i) Mod-10 Counter

CLK Qd Qc Qb Qa
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
ii) Mod-5 Counter

Logic DiagramTruthtable
CLK Qd Qc Qb Qa
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0

iii) Mod-2 Counter

Logic DiagramTruth table
CLK Qd Qc Qb Qa
0 0 0 0 0
1 0 0 0 1
iii) Mod-6 Counter
Logic DiagramTruth table
CLK Qd Qc Qb Qa
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1

Aim: To realize the mod-N synchronous counter using IC-74192

1 IC74192 1
2 IC7408 1
3 IC7400 1
4 IC7432 1
5 Patch cords 1 set
6 IC trainer Kit 1
Theory:
The 74HC192 is asynchronously preset table BCD Decade and Binary

Up/Down synchronous counters, respectively. Presetting the counter to the
number on the preset data inputs (P0-P3) is accomplished by a LOW
asynchronous parallel load input (PL)\. The counter is incremented on the
low-to-high transition of the Clock-Up input (and a high level on the Clock-
Down input) and decremented on the low to high transition of the Clock-
Down input (and a high level on the Clock-up input). A high level on the MR
input overrides any other input to clear the counter to its zero state. The
Terminal Count up (carry) goes low half a clock period before the zero count
is reached and returns to a high level at the zero count. The Terminal
Count Down (borrow) in the count down mode likewise goes low half a clock
period before the maximum count (9 in the 192 ) and returns to high at the
maximum count. Cascading is effected by connecting the carry and borrow
outputs of a less significant counter to the Clock-Up and CLock-Down
inputs, respectively, of the next most significant counter.

Pin Configuration


Demonstration Experiments( For CIE)

Experiment- 9
Aim:To Design a Monostable Multivibrator using a IC-555 Timer togenerate
a square wave of desired pulse width.
1 IC555 - 1
2 Resistors 36.36 K Ω 1
3 Capacitors 0.1 µF, 0.01 µF 1 each
4 DRB - 1
5 DC Supply - 1
6 CRO - 1
7 Bread Board - 1
8 CRO Probes - 2
9 Connecting wires - 1 set
Theory:
The 555 timer is a highly stable device for generating accurate time
delay.The internal structure of 555 is shown in which there are two
comparators, a flip flop, an output stage, a voltage divider network and a
transistor. The comparator is a device whose output is high when the non-
inverting input voltage is greater than inverting input voltage and output is
low when inverting input voltage is greater than non-inverting input voltage.
The voltage divider network consist of three 5KΩ resistors and provides a
trigger voltage level of 1/3VCC and threshold voltage level of 2/3VCC.The
control voltage is used for changing the threshold and trigger voltages
externally.The monostable multivibrator has one stable state and one quasi
stable state. Monostable multivibrator produces an output pulse with
defined time period for each external trigger pulse applied. It comes out of
the stable state only by use of an external signal called trigger. When the
output is low, that is, the circuit is in stable state. Upon application of
trigger pulse to pin 2, the output of the comparator II becomes high which
sets the flip flop high. As the output is high, the transistor becomes OFF
since it is connected to the Q - of the flip flop.

Circuit Design:
Given pulse width W = 4 msec
Choose C=0.01µF
Circuit Diagram:

Waveforms:
Procedure:
2. Trigger pulses are applied at the input pin no 2(The duty cycle of
trigger pulses is adjusted so off time is less than pulse width).
3. The pulse width of the waveforms at pin 3 is measured and verified
with the desired value.
4. The pulse width of the waveforms at pin 3 is measured and verified
with the desired value.
5. Capacitor voltage waveforms are observed at pin 2 or 6.
Result:
Pulse width given w = 4 m sec
Pulse width observed w =

Aim: To Design a Astable Multivibrator using a IC555 Timer to generate a

square wave of desired frequency and duty cycle.
1 IC555 - 1
2 Capacitors 0.1 µF, 0.01 µF 1 each
3 DRB - 1
4 DC Supply - 1
5 CRO - 1
6 Bread Board - 1
7 CRO Probes - 2
8 Connecting - 1 set
wires
Theory:
Astable multivibrator means it has no stable states. It has two quasi stable
states (high and low).In the figure given, there are 2 external resistors RA
and RB and a capacitor C. When the power is given to the circuit the
capacitor C will charge towards VCC through RA and RB, when the
capacitor voltage exceeds the level of (2/3)VCC (threshold voltage) the
output of the comparator I goes high which resets the flip flop so the output
Q of the flip-flop becomes low and Q - becomes high. Now the transistor
which is connected to Q - becomes ON. The capacitor C started to discharge
through RB and transistor exponentially. When voltage across capacitor
reaches just below of (1/3)VCC (trigger voltage) the output of the comparator
II becomes high and sets the flip flop, turning OFF the transistor since it is
connected to the Q - of the flip flop. The capacitor C will begin to charge
towards VCC through RA and RB. when the capacitor voltage exceeds the
level of (2/3)VCC, the output of the comparator I goes high which resets the
flip-flop so the output Q of the flip flop becomes low and Q - becomes high.
The cycle continues which gives a square wave at the output (pin 3) and
charging and discharging wave form across capacitor (pin 2&6).
Circuit Design:
Assume f = 2 kHz and duty cycle of 70 %.
Consider C = 0.1 µF.
D = RA/(RA+RB)

Circuit Diagram:
Waveforms:

Procedure:
1. Circuit is rigged up as shown in figure.
2. Output voltage waveform is observed at pin 3 of the IC 555 and are
traced.
3. Capacitor voltage waveform is observed at pin 2 or 6 and are traced.
4. Ton, Toff and T of the output waveform at pin3 are measured and
verified.
Result:
Astable multivibrator has been designed and tested.
Parameters Theoretical value Practical value

Frequency
Duty cycle

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DEPARTMENTOFELECTRONICS

IIISEMESTER LAB MANUAL

Analog and Digital System Design

Vision and Mission of the Institute

Vision of the Institute

Mission of the Institute

• To mould engineers and managers with appropriate pedagogy to

• To develop student-centric institution which evolves and fosters the

• To promote Research and Consultancy through collaboration with

Department of ECE, GMIT, Davangere Page2

Vision, Mission, PEOs & PSOs of the Department

Vision of the Department

Mission of the Department

Program Educational Objectives

PEO1: To deliver Engineering Skills and Knowledge by integrating basic

Program Specific Outcomes

PSO1: Design Analog and Digital Systems using emerging Technologies.

PSO2: Build different models by applying Technical knowledge

Department of ECE, GMIT, Davangere Page3

Graduates of Electronics & Communication Engineering by the time of

PO1: Engineering knowledge: Apply the knowledge of mathematics, science,

Analog and Digital Electronics Lab-21ECL35

Sl.No. List of Experiments

Demonstration Experiments( For CIE)

Design and test the following using 555timer

Department of ECE, GMIT, Davangere Page5

Course outcomes (Course Skill Set):

Assessment Details (both CIE and SEE)

Continuous Internal Evaluation (CIE):

• Each experiment to be evaluated for conduction with observation sheet and

Department of ECE, GMIT, Davangere Page6

experiment write-upwill be evaluated for 10 marks.

Evaluation of test write-up/ conduction procedure and result/viva will be

General rubrics suggested for SEE are mentioned here, writeup-20%,

5th Edition, 2009, OxfordUniversity Press.

1. Start the experiment as per the procedure.

1. Calculate all required quantities and enter in the tabulation.

Department of ECE, GMIT, Davangere Page8

Department of ECE, GMIT, Davangere Page9

Sl No Components Specification Quantity

Department of ECE, GMIT, Davangere Page10

Collectror through the capacitor cc2.

The input impedance of the amplifier is expressed as Zin=R1||R2||(1+hFEre) and

Quick Reference data of BC107

Application: In audio frequency

Maximum rating: VCB=50V,VCE=45V,VEB=6V,IC=100mA.

Nominal rating: VCE=5V, IC=2mA, hFE=100 to 500.

DC b i as i n g conditions VCC is taken as 20% more than required output swing.

From this, we get RC =2.4k, Use2.2k.

Department of ECE, GMIT, Davangere Page11

Design of voltage divider R1 and R2

i.e., VR2=VBE+VRE=0.6+1.2=1.8V. Also, VR2=9IBR2 =1.8V

But IB= IC/hFE = 2mA/100 = 20µA.

Then R = 1.8 / 9×20×10-6 = 10.6k, Use10k.

VR1=voltage across R1 =VCC-VR2=12V -1.8V =10.2V

Also, V = 10IR =10.1V.

Then R= 10.2/ (10×20×10-6) = 50k. Select 47k std.

Design of coupling capacitors CC1 and CC2

R2 = VR2/ 9IB = 1.8/(92010-6) = 10K