Logic and Computer Design Fundamentals

Chapter 3 – Combinational
Logic Design
Part 1 – Implementation Technology and Logic
Design
 Combinational Circuits
▪ A combinational logic circuit has:
• A set of m Boolean inputs,
• A set of n Boolean outputs, and
• n switching functions, each mapping the 2m input
combinations to an output such that the current output
depends only on the current input values
▪ A block diagram:
Combinatorial
Logic
Circuit

m Boolean Inputs n Boolean Outputs

Design Procedure
1. Specification
• Write a specification for the circuit if one is not already
available
2. Formulation
• Derive a truth table or initial Boolean equations that define the
required relationships between the inputs and outputs.
3. Optimization
• Apply 2-level and multiple-level optimization
4. Draw a logic diagram or provide a netlist for the resulting circuit
using ANDs, ORs, and invertersTechnology Mapping
• Map the logic diagram or netlist to the implementation
technology selected
5. Verification
• Verify the correctness of the final design manually or using
simulation
 Design Example
1. Specification
• BCD to Excess-3 code converter
• Transforms BCD code for the decimal digits to
Excess-3 code for the decimal digits
• BCD code words for digits 0 through 9: 4-bit
patterns 0000 to 1001, respectively
• Excess-3 code words for digits 0 through 9: 4-
bit patterns consisting of 3 (binary 0011) added
to each BCD code word
• Implementation:
▪ multiple-level circuit
▪ NAND gates (including inverters)
 Design Example (continued)
2. Formulation
• Conversion of 4-bit codes can be most easily
formulated by a truth table
• Variables Input BCD Output Excess-3
- BCD: ABCD WXYZ
A,B,C,D 0000 0011
0001 0100
• Variables
0010 0101
- Excess-3 0011 0110
W,X,Y,Z 0100 0111
• Don’t Cares 0101 1000
0110 1001
- BCD 1010 0111 1010
to 1111 1000 1011
1001 1011
Design Example (continued)
C C
3. Optimization z 1 1
y
1 1
0 1 3 2 0 1 3 2

a. 2-level using 1
4 5 7
1
6
1
4 5
1
7 6

K-maps X X X X B X X X X B
12 13 15 14 12 13 15 14

W = A + BC + BD A 1 X X A 1 X X
8 9 11 10 8 9 11 10

X = B C + B D + BC D D D
Y = CD + C D
Z=D x C C
w
1 1 1
0 1 3 2 0 1 3 2

1 1 1 1
4 5 7 6 4 5 7 6

X X X X B X X X X B
12 13 15 14 12 13 15 14

A 1 X X A 1 1 X X
8 9 11 10 8 9 11 10

D D
 Design Example (continued)
4. Technology Mapping
• Mapping with a library containing inverters and 2-input
NAND, 2-input NOR, and 2-2 AOI gates
A A
W
W

B X
B

X
C

C Y
D D Y
Z

Z
Verification
▪ Verification - show that the final circuit
designed implements the original specification
▪ Simple specifications are:
• truth tables
• Boolean equations
• HDL code
▪ If the above result from formulation and are
not the original specification, it is critical that
the formulation process be flawless for the
verification to be valid!
Basic Verification Methods
▪ Manual Logic Analysis
• Find the truth table or Boolean equations for the final circuit
• Compare the final circuit truth table with the specified truth
table, or
• Show that the Boolean equations for the final circuit are equal
to the specified Boolean equations
▪ Simulation
• Simulate the final circuit (or its netlist, possibly written as an
HDL) and the specified truth table, equations, or HDL
description using test input values that fully validate
correctness.
• The obvious test for a combinational circuit is application of all
possible “care” input combinations from the specification
Verification Example: Manual Analysis
▪ BCD-to-Excess 3 Code Converter
• Find the SOP Boolean equations from the final
circuit.
• Find the truth table from these equations
• Compare to the formulation truth table
▪ Finding the Boolean Equations:
T1 = C + D = C + D
W = A (T1 B) = A + B T1
X = (T1 B) (B C D) = B T1 + B C D
Y = C D + C D = CD + CD
Verification Example: Manual Analysis
▪ Find the circuit truth table from the equations and compare
to specification truth table:
Input BCD Output Excess-3
AB C D WXYZ
0000 0011
0001 0100
0010 0101
0011 0110
0100 0111
0101 1000
0110 1001
0111 1010
1000 1011
1001 1011
The tables match!
Top-Down versus Bottom-Up
▪ A top-down design proceeds from an abstract, high-
level specification to a more and more detailed design
by decomposition and successive refinement
▪ A bottom-up design starts with detailed primitive blocks
and combines them into larger and more complex
functional blocks
▪ Design usually proceeds top-down to known building
blocks ranging from complete CPUs to primitive logic
gates or electronic components.
▪ Much of the material in this chapter is devoted to
learning about combinational blocks used in top-down
design.
Hierarchical Design
X0
X1
X2
X3 9-Input
X4 odd ZO
X5 function
X6 X0 A0
X7 3-Input
X8 X1 A1 odd B O
function
(a) Symbol for circuit X2 A2

X3 A0 A0
3-Input 3-Input
X4 A 1 odd B O A1 odd B
O ZO
function function
X5 A2 A2

X6 A0
3-Input
X7 A1 odd B O
function
X8 A2

(b) Circuit as interconnected 3-input odd

function blocks
A0
A1 BO

A2

(c) 3-input odd function circuit as

interconnected exclusive-OR
blocks

(d) Exclusive-OR block as interconnected

NANDs
NAND Mapping Algorithm
1. Replace ANDs and ORs:
. .
. .
. .

. .
. .
. .

2. Repeat the following pair of actions until there

is at most one inverter between :
a. A circuit input or driving NAND gate output, and
b. The attached NAND gate inputs.

. .
. .
. .
NAND Mapping Example
NOR Mapping Algorithm
1. Replace ANDs and ORs:
. .
. .
. .

. .
. .
. .

2. Repeat the following pair of actions until there

is at most one inverter between :
a. A circuit input or driving NAND gate output, and
b. The attached NAND gate inputs.

. .
. .
. .
 NOR Mapping Example

A A
B
B
2
X
F 1
C F
C
3
D
D
E
(a) A E
(b)
B

C
F
D
E
(c)
 Integrated Circuits

Integrated Circuits(IC)
◆ Digital circuits are constructed with Integrated Circuits
◆ An Integrated Circuits is a small silicon semiconductor crystal,
called chip
◆ The various gates are interconnected inside the chip to form the
required circuit
◆ The chip is mounted in a ceramic or plastic container, and
connections are welded by thin gold wires to external pins to form
the integrated circuits
◆ The number of pins may range from 14 in a small IC package to
100 or more in a larger package
◆ Each IC has a numeric designation printed on the surface of the
package for identification
The number of gates that can be put in a single chip has increased.
SSI: Small Scale Integration devices contain several independent
gates in a single package.
◆ The input and outputs of the gates are directly connected to the
pins in the package
MSI: Medium scale integration devices – decoders, adders and
registers
LSI: Large-scale integration devices – processors, memory chips,…
VLSI: Very large scale integration devices- large memory arrays and
complex microcomputer chips.
Different logic Families of IC
TTL Family – considered as standard
ECL Family- high speed operation
MOS Family : High Component Density
CMOS Family: Low Power consumption
Enabling Function
▪ Enabling permits an input signal to pass
through to an output
▪ Disabling blocks an input signal from passing
through to output, replacing it with a fixed
value

X
F
EN
▪ When disabled, 0 output (a)
▪ When disabled, 1 output
X
F
EN

(b)
Decoding
▪ Decoding - the conversion of an n-bit input
code to an m-bit output code with
n  m  2n such that each valid code word
produces a unique output code
▪ Circuits that perform decoding are called
decoders
▪ Here, functional blocks for decoding are
• called n-to-m line decoders, where m  2n, and
• generate 2n (or fewer) minterms for the n input
variables
Decoder Examples
▪ 1-to-2-Line DecoderA D0 D1
D0 5 A
0 1 0
1 0 1 A D1 5 A
▪ 2-to-4-Line Decoder (a) (b)
A0
A1 A0 D0 D1 D2 D3
A1
0 0 1 0 0 0 D0 5 A 1 A 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1 D1 5 A 1 A 0

(a)
D2 5 A 1 A 0
▪ Note that the 2-4-line
made up of 2 1-to-2- D3 5 A 1 A 0
line decoders and 4 AND gates.
(b)
 Decoder Expansion - Example 1
▪ 3-to-8-line decoder
• Number of output ANDs = 8
• Number of inputs to decoders driving output ANDs = 3
• Closest possible split to equal
▪ 2-to-4-line decoder
▪ 1-to-2-line decoder
• 2-to-4-line decoder
▪ Number of output ANDs = 4
▪ Number of inputs to decoders driving output ANDs = 2
▪ Closest possible split to equal
• Two 1-to-2-line decoders
Decoder Expansion - Example 1
▪ Result
Decoder Expansion - Example 2
▪ 7-to-128-line decoder
• Number of output ANDs = 128
• Number of inputs to decoders driving output ANDs
=7
• Closest possible split to equal
▪ 4-to-16-line decoder
▪ 3-to-8-line decoder
• 4-to-16-line decoder
▪ Number of output ANDs = 16
▪ Number of inputs to decoders driving output ANDs = 2
▪ Closest possible split to equal
• 2 2-to-4-line decoders
• Complete using known 3-8 and 2-to-4 line decoders
 Decoder with Enable
▪ In general, attach m-enabling circuits to the outputs
▪ See truth table below for function
• Note use of X’s to denote both 0 and 1
• Combination containing two X’s represent four binary combinations
▪ Alternatively, can be viewed as distributing value of signal
EN
EN to 1 of 4 outputs
A 1

▪ In this case, called a

A 0
demultiplexer D 0

EN A 1 A 0 D0 D1 D2 D3 D1

0 X X 0 0 0 0
1 0 0 1 0 0 0 D2
1 0 1 0 1 0 0
1 1 0 0 0 1 0
D3
1 1 1 0 0 0 1

(a) (b)
 Decoder/Encoder

Decoder
◆ A combinational circuit that converts binary information from the n
coded inputs to a maximum of 2n unique outputs
◆ n-to-m line decoder = n x m decoder
n inputs, m outputs
◆ If the n-bit coded information has unused bit combinations, the decoder
may have less than 2n outputs
m  2n
3-to-8 Decoder
◆ Commercial decoders include one or more Enable Input(E)
 Decoder

3-to-8 Decoder
Enable Inputs Outputs A2
E A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 A1 D0
0 x x x 0 0 0 0 0 0 0 0 A0
D1
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0 D2
1 0 1 0 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 1 0 0 0 D3

1 1 0 0 0 0 0 1 0 0 0 0 D4
1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 1 0 0 0 0 0 0 D5
1 1 1 1 1 0 0 0 0 0 0 0
D6
Truth table for 3-to-8 Decoder
D7

Enable(E)
 Decoder Expansion

Decoder Expansion
◆ 3 X 8 Decoder constructed with two 2 X 4 Decoder

0
A0 2
1 5

D0
a1 b1

1
2
A1 2
a2

2 X4
b2
6

D1
Decoder
A2 3
a3
E
b3
7
D2
b4
8 D3

0
2
1 5
a1 b1

1
D4
2
a2 2 b2
6

2 X4 D5
Decoder
E
3 7
a3 b3

D6
b4
8

D7

A 3-to-8 Decoder
constructed with two
with 2-to-4 Decoder
 Encoding
▪ Encoding - the opposite of decoding - the conversion
of an m-bit input code to a n-bit output code with n 
m  2n such that each valid code word produces a
unique output code
▪ Circuits that perform encoding are called encoders
▪ An encoder has 2n (or fewer) input lines and n output
lines which generate the binary code corresponding
to the input values
▪ Typically, an encoder converts a code containing
exactly one bit that is 1 to a binary code corres-
ponding to the position in which the 1 appears.
 Encoder

Encoder
◆ Inverse Operation of a decoder
◆ 2n input, n output
◆ Truth Table :
3 OR Gates Implementation
» A0 = D1 + D3 + D5 + D7 Example of an encoder
» A1 = D2 + D3 + D6 + D7
» A2 = D4 + D5 + D6 + D7
is the octal-to-binary
encoder
Truth Table for Encoder

Inputs Outputs
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
 Multiplexers

Multiplexer(Mux)
◆ A combinational circuit that receives binary information from one of 2n
input data lines and directs it to a single output line
◆ A 2n –to -1 multiplexer has 2n input data lines and
n input selection lines(Data Selector)
◆ 4-to-1 multiplexer Diagram
◆ 4-to-1 multiplexer Function Table
I0

I1
Y

I2
Select Output
S1 S0 Y I3
0 0 I0
Function Table for
0 1 I1
4-to-1 line Multiplexter 1 0 I2 S0
1 1 I3 S1
4-to-1 Line Multiplexer
Quadruple 2-to-1 Multiplexer
◆ Quadruple 2-to-1 Multiplexer
◆ The circuit has 4 Muxs, each capable of selecting one of two inputs.
◆ An enable may be used, it must be active for normal operation

Enable
Select

A0 Y0
Select Output A1 Quadruple Y1
A2 2x1 Y2
E S Y A3 Mux Y3
Quadruple 2-to-1
0 0 All 0's B0
line Multiplexter B1
1 0 A B2
B3
1 1 B
(a) Function Table

(b) Block Diagram

Multiplexers
▪ A multiplexer selects information from
an input line and directs the information
to an output line
▪ A typical multiplexer has n control inputs
(Sn - 1, … S0) called selection inputs, 2n
information inputs (I2n - 1, … I0), and one
output Y
▪ A multiplexer can be designed to have m
information inputs with m < 2n as well as
n selection inputs
2-to-1-Line Multiplexer
▪ Since 2 = 21, n = 1
▪ The single selection variable S has two values:
• S = 0 selects input I0
• S = 1 selects input I1
▪ The equation:
Y = S I0 + SI1
Enabling
▪ The circuit: Decoder Circuits

I0
Y
S
I1
Iterative Combinational Circuits
▪ Arithmetic functions
• Operate on binary vectors
• Use the same subfunction in each bit position
▪ Can design functional block for subfunction
and repeat to obtain functional block for
overall function
▪ Cell - subfunction block
▪ Iterative array - a array of interconnected cells
▪ An iterative array can be in a single dimension
(1D) or multiple dimensions
Block Diagram of a 1D Iterative Array

▪ Example: n = 32
• Number of inputs = ?
• Truth table rows = ?
• Equations with up to ? input variables
• Equations with huge number of terms
• Design impractical!
▪ Iterative array takes advantage of the regularity to
make design feasible
Functional Block: Half-Adder
▪ A 2-input, 1-bit width binary adder that performs the
following computations:
X 0 0 1 1
+Y +0 +1 +0 +1
CS 00 01 01 10
▪ A half adder adds two bits to produce a two-bit sum
▪ The sum is expressed as a X Y C S
sum bit , S and a carry bit, C 0 0 0 0
▪ The half adder can be specified 0 1 0 1
as a truth table for S and C 
1 0 0 1
1 1 1 0
Logic Simplification: Half-Adder
▪ The K-Map for S, C is:
S = XY’ +X’Y S Y C Y
S= X  Y 0 11 0 1

C=XY X 12 3 X 2 13
 Functional Block: Full-Adder
▪ A full adder is similar to a half adder, but includes a
carry-in bit from lower stages. Like the half-adder, it
computes a sum bit, S and a carry bit, C.
• For a carry-in (Z) of Z 0 0 0 0
0, it is the same as X 0 0 1 1
the half-adder: +Y +0 +1 +0 +1
CS 00 01 01 10
• For a carry- in
(Z) of 1: Z 1 1 1 1
X 0 0 1 1
+Y +0 +1 +0 +1
CS 01 10 10 11
Logic Optimization: Full-Adder
▪ Full-Adder Truth Table: X Y Z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
▪ Full-Adder K-Map: 1 1 0 1 0
1 1 1 1 1

S Y C Y
1 1 1
0 1 3 2 0 1 3 2

X 1 1 X 1 1 1
4 5 7 6 4 5 7 6

Z Z
Equations: Full-Adder
▪ From the K-Map, we get:
S = XYZ+ XY Z+ XYZ+ XYZ
C = XY+XZ+YZ
▪ The S function is the three-bit XOR function (Odd
Function):
S = XYZ
▪ The Carry bit C is 1 if both X and Y are 1 (the sum is
2), or if the sum is 1 and a carry-in (Z) occurs. Thus C
can be re-written as:
C = X Y + (X  Y) Z
Logic Diagram: Full Adder

X
Y S

Z
4-bit Ripple-Carry Binary Adder

▪ A four-bit Ripple Carry Adder made from four

1-bit Full Adders:
B3 A3 B2 A2 B1 A1 B0 A0

C3 C2 C1
FA FA FA FA C0

C4 S3 S2 S1 S0
Unsigned Subtraction
▪ Algorithm:
• Subtract the subtrahend N from the minuend M
• If no end borrow occurs, then M  N, and the result
is a non-negative number and correct.
• If an end borrow occurs, the N > M and the
difference M - N + 2n is subtracted from 2n, and a
minus sign is appended to the result.
0 1
▪ Examples:
1001 0100
- 0111 - 0111
0010 1101
10000
- 1101
(-) 0011
Complements
▪ Two complements:
• Diminished Radix Complement of N
▪ (r - 1)’s complement for radix r
▪ 1’s complement for radix 2
▪ Defined as (rn - 1) - N
• Radix Complement
▪ r’s complement for radix r
▪ 2’s complement in binary
▪ Defined as rn - N
▪ Subtraction is done by adding the complement of
the subtrahend
▪ If the result is negative, takes its 2’s complement
Binary 1's Complement
▪ For r = 2, N = 011100112, n = 8 (8 digits):
(rn – 1) = 256 -1 = 25510 or 111111112
▪ The 1's complement of 011100112 is then:
11111111
– 01110011
10001100
▪ Since the 2n – 1 factor consists of all 1's and
since 1 – 0 = 1 and 1 – 1 = 0, the one's
complement is obtained by complementing
each individual bit (bitwise NOT).
Binary 2's Complement
▪ For r = 2, N = 011100112, n = 8 (8 digits),
we have:
(rn ) = 25610 or 1000000002
▪ The 2's complement of 01110011 is then:
100000000
– 01110011
10001101
▪ Note the result is the 1's complement plus
1, a fact that can be used in designing
hardware
Alternate 2’s Complement Method
▪ Given: an n-bit binary number, beginning at the
least significant bit and proceeding upward:
• Copy all least significant 0’s
• Copy the first 1
• Complement all bits thereafter.
▪ 2’s Complement Example:
10010100
• Copy underlined bits:
100
• and complement bits to the left:
01101100
Subtraction with 2’s Complement
▪ For n-digit, unsigned numbers M and N, find M
- N in base 2:
• Add the 2's complement of the subtrahend N to
the minuend M:
M + (2n - N) = M - N + 2n
• If M  N, the sum produces end carry 2n which is
discarded, M - N remains.
• If M < N, the sum does not produce an end carry.
2n - ( N - M ), the 2's complement of ( N - M ).
• To obtain the result - (N – M) , take the 2's
complement of the sum and place a - to its left.
Unsigned 2’s Complement Subtraction Example 1

▪ Find 010101002 – 010000112

01010100 1 01010100
– 01000011 2’s comp + 10111101
00010001
▪ The carry of 1 indicates that no
correction of the result is required.
Unsigned 2’s Complement Subtraction Example 2

▪ Find 010000112 – 010101002

0
01000011 01000011
– 01010100 2’s comp + 10101100
11101111 2’s comp
00010001
▪ The carry of 0 indicates that a correction
of the result is required.
▪ Result = – (00010001)
Signed Integers
▪ Positive numbers and zero can be represented by
unsigned n-digit, radix r numbers. We need a
representation for negative numbers.
▪ To represent a sign (+ or –) we need exactly one more
bit of information (1 binary digit gives 21 = 2 elements
which is exactly what is needed).
▪ Since computers use binary numbers, by convention,
the most significant bit is interpreted as a sign bit:
s an–2  a2a1a0
where:
s = 0 for Positive numbers
s = 1 for Negative numbers
and ai = 0 or 1 represent the magnitude in some form.
Signed Integer Representations

▪Signed-Magnitude – here the n – 1 digits are

interpreted as a positive magnitude.
▪Signed-Complement – here the digits are
interpreted as the rest of the complement of the
number. There are two possibilities here:
• Signed 1's Complement
▪ Uses 1's Complement Arithmetic
• Signed 2's Complement → most common
▪ Uses 2's Complement Arithmetic
Signed-magnitude system
▪ Examples:
▪ 00001001 → 9 (unsigned) or +9 (signed)
▪ In signed-magnitude (-9)→ 10001001
▪ In signed 2’s complement (-9)→ 11110111
Signed Integer Representation Example

▪ r =2, n=3

Number Sign -Mag. 1's Comp. 2's Comp.

+3 011 011 011
+2 010 010 010
+1 001 001 001
+0 000 000 000
–0 100 111 —
–1 101 110 111
–2 110 101 110
–3 111 100 101
–4 — — 100
Signed-Complement Arithmetic
▪ Addition:
1. Add the numbers including the sign bits,
discarding a carry out of the sign bits (2's
Complement), or using an end-around carry (1's
Complement).
2. If the sign bits were the same for both
numbers and the sign of the result is different, an
overflow has occurred.
3. The sign of the result is computed in step 1.
▪ Subtraction:
Form the complement of the number you are
subtracting and follow the rules for addition.
Adder-Subtractor Circuit

B3 A3 B2 A2 B1 A1 B0 A0

C3 C2 C1 C0
FA FA FA FA

C4 S3 S2 S1 S0
2’s Complement Adder/Subtractor
▪ Subtraction can be done by addition of the 2's
Complement.
1. Complement each bit (1's Complement.)
2. Add 1 to the result.
▪ The circuit shown computes A + B and A – B:
▪ For S = 1, subtract, the 2’s complement of B is formed by
using XORs to form the 1’s comp and adding the 1 applied
to C0.
▪ For S = 0, add, B is passed through unchanged
Signed 2’s Complement Examples
▪ Example 1: 1101
+0011
1 0000 carry out is discarded

▪ Example 2: 1101 1101

-0011 →2’s 1101
1010
Overflow Detection
▪ Overflow occurs if n + 1 bits are required to contain the
result from an n-bit addition or subtraction
▪ Overflow can occur for:
• Addition of two operands with the same sign
• Subtraction of operands with different signs
▪ Signed number overflow cases with correct result sign
0 0 1 1
+0 -1 - 0 +1
0 0 1 1
▪ Detection can be performed by examining the result
signs which should match the signs of the top operand
Overflow Detection
▪ Signed number cases with carries Cn and Cn-1 shown for correct
result signs:
0 00 01 11 1
0 0 1 1
+ 0 -1 - 0 + 1
0 0 1 1
▪ Signed number cases with carries shown for erroneous result signs
(indicating overflow):
0 10 11 01 0
0 0 1 1
+ 0 - 1 -0 + 1
1 1 0 0
▪ Simplest way to implement overflow V = Cn + Cn - 1
▪ This works correctly only if 1’s complement and the addition of
the carry in of 1 is used to implement the complementation!
Otherwise fails for - 10 ... 0
Overflow

V Cn-1
n-bit Adder/ subtractor

C Cn
Other Arithmetic Functions
▪ Convenient to design the functional
blocks by contraction - removal of
redundancy from circuit to which input
fixing has been applied
▪ Functions
• Incrementing
• Decrementing
• Multiplication by Constant
• Division by Constant
 Incrementing & Decrementing
▪ Incrementing
• Adding a fixed value to an arithmetic variable
• Fixed value is often 1, called counting (up)
• Examples: A + 1, B + 4
• Functional block is called incrementer
▪ Decrementing
• Subtracting a fixed value from an arithmetic variable
• Fixed value is often 1, called counting (down)
• Examples: A - 1, B - 4
• Functional block is called decrementer