UC1625-SP

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RAD-TOLERANT CLASS V, BRUSHLESS DC MOTOR CONTROLLER

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1FEATURES • High-speed Current-Sense Amplifier with Ideal

• QML-V Qualified, SMD 5962-91689 Diode
• Rad-Tolerant: 40 kRad (Si) TID (1) • Pulse-by-Pulse and Average Current Sensing
• Drives Power MOSFETs or Power Darlingtons • Over-Voltage and Under-Voltage Protection
Directly • Direction Latch for Safe Direction Reversal
• 50-V Open Collector High-Side Drivers • Tachometer
• Latched Soft Start • Trimmed Reference Sources 30 mA
(1) Radiation tolerance is a typical value based upon initial device • Programmable Cross-Conduction Protection
qualification with dose rate = 10 mrad/sec. Radiation Lot • Two-Quadrant and Four-Quadrant Operation
Acceptance Testing is available - contact factory for detials.

DESCRIPTION/ORDERING INFORMATION
The UC1625 motor controller integrates most of the functions required for high-performance brushless dc motor
control into one package. When coupled with external power MOSFETs or Darlingtons, this device performs
fixed-frequency PWM motor control in either voltage or current mode while implementing closed loop speed
control and braking with smart noise rejection, safe direction reversal, and cross-conduction protection.
Although specified for operation from power supplies between 10 V and 18 V, the UC1625 can control higher
voltage power devices with external level-shifting components. The UC1625 contains fast, high-current push-pull
drivers for low-side power devices and 50-V open-collector outputs for high-side power devices or level shifting
circuitry.
The UC1625 is characterized for operation over the military temperature range of –55°C to 125°C.

ORDERING INFORMATION (1)

ORDERABLE PART
TA PACKAGE (2) TOP-SIDE MARKING
NUMBER
5962-9168902VYA
–55°C to 125°C CDIP – JT 5962-9168902VYA
UC1625-SP

(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI website at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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Typical Application
+5 V TO HALL +15 V VMOTOR
VREF
SENSORS

3 kW +
100 nF 100 nF + 100 mF
2N3904
20 mF
20 mF 10 W
10 kW
3 kW 10 kW
ROSC 2 19 11
QUAD 33 kW 2N3906
IRF9350
22 3 kW
DIR
16
6 TO
1k 17 MOTOR
1 TO OTHER
100 nF
CHANNELS
18
28 UC1625
UC3625
4 kW
14 REQUIRED
27 TO OTHER FOR BRAKE
CHANNELS AND FAST
13
25 10 W REVERSE
2200 pF IRF532
12
COSC
15 20

BRAKE 21 26 3 24 23 8 9 10 4 5 7 10 kW

100 nF
5 nF
3 nF 68 kW REQUIRED
CT RT 240 W FOR
100 nF FROM HALL
AVERAGE
SENSORS 0.02 W
2 nF CURRENT
5 nF 240 W RS SENSING
51 kW 2 nF
0.02 W
2 nF RD

VREF

ABSOLUTE MAXIMUM RATINGS (1) (2)

over operating free-air temperature range (unless otherwise noted)

VALUE UNIT
VCC 20
Supply voltage
PWR VCC 20
PWM IN –0.3 to 6
E/A IN(+), E/A IN(–) –0.3 to 12
V
ISENSE1, ISENSE2 –1.3 to 6
OV-COAST, DIR, SPEED-IN, SSTART, QUAD SEL –0.3 to 8
H1, H2, H3 –0.3 to 12
PU Output Voltage –0.3 to 50
PU +200 continuous
PD ±200 continuous
E/A ±10
Output current mA
ISENSE –10
TACH OUT ±10
VREF –50 continuous
TJ Maximum Junction Temperature 150 °C

(1) Currents are positive into and negative out of the specified terminal.
(2) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only and functional operation of the device at these or any other conditions beyond
those specified is not implied.

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RECOMMENDED OPERATING CONDITIONS

over operating temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply Voltage 10 18 V
PU Output Current +85 mA
continuous
PD ±85 mA
continuous
TA Operating temperature range -55 125 °C

Table 1. THERMAL RATINGS TABLE

RθJA(°C/W) RθJC(°C/W)
PACKAGE
(Junction-to-ambient thermal resistance) (Junction-to-case thermal resistance)
DIL-28 (JT) 43.1 4.95

Figure 1. CONNECTION DIAGRAM

E/A IN(+) 1 28 E/A IN(-)

VREF 2 27 E/A OUT

ISENSE 3 26 PWM IN

ISENSE1 4 25 RC-OSC

ISENSE2 5 24 SSTART

DIR 6 23 OV-COAST

SPEED-IN 7 22 QUAD SEL

H1 8 21 RC-BRAKE

H2 9 20 TACH-OUT

H3 10 19 VCC

PWR VCC 11 18 PUA

PDC 12 17 PUB

PDB 13 16 PUC

PDA 14 15 GND

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ELECTRICAL CHARACTERISTICS
Unless otherwise stated, these specifications apply over the full temperature range, typical values at TA = 25°C; Pwr VCC =
VCC = 12 V; ROSC = 20 kΩ to VREF; COSC = 2 nF; RTACH = 33 kΩ; CTACH = 10 nF; and all outputs unloaded. TA = TJ.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Overall
Supply current 14.5 30.0 mA
VCC turn-on threshold -55°C to 125°C 8.65 8.95 9.55
V
VCC turn-off threshold 7.75 8.05 8.55
Overvoltage/Coast
OV-COAST inhibit threshold 1.65 1.75 1.85
OV-COAST restart threshold 1.535 1.65 1.75 V
-55°C to 125°C
OV-COAST hysteresis 0.05 0.10 0.155
OV-COAST input current –10 –1 10 μA
Logic Inputs
H1, H2, H3 low threshold 0.8 1.0 1.25
-55°C to 125°C V
H1, H2, H3 high threshold 1.6 1.9 2.0
H1, H2, H3 input current -55°C to 125°C, to 0 V –400 –250 –120 μA
QUAD SEL, dir thresholds 0.8 1.4 3.0 V
QUAD SEL hysteresis 70 130 mV
DIR hysteresis -55°C to 125°C 0.4 0.6 0.9 V
QUAD SEL input current –30 50 150
μA
DIR input current –30 –1 30
PWM Amp/Comparator
E/A IN(+), E/A IN(–) input current To 2.5 V –5.0 –0.1 5.0
μA
PWM IN input current To 2.5 V 0 3 30
Error amp input offset 0 V < VCOMMON-MODE < 3 V –10 10 mV
Error amp voltage gain 70 90 dB
E/A OUT range 25°C to 125°C 0.25 3.50
V
-55°C 0.25 4.2
Pullup current To 0 V, 25°C -16 –10 –5
μA
To 0 V , -55°C to 125°C –17.5 -5
SSTART
Discharge current To 2.5 V 0.1 0.4 3.0 mA
Restart threshold 0.1 0.2 0.3 V
Current Amp
Gain ISENSE1 = 0.3 V, ISENSE2 = 0.5 V to 0.7 V 1.75 1.95 2.15 V/V
Level shift ISENSE1 = 0.3 V, ISENSE2 = 0.3 V 2.4 2.5 2.65
Peak current threshold 0.14 0.20 0.26 V
ISENSE1 = 0 V, force ISENSE2
Over current threshold 0.26 0.30 0.36
ISENSE1, ISENSE2 input current –850 –320 0
To 0 V μA
ISENSE1, ISENSE2 offset current -12 ±2 12
Range ISENSE1, ISENSE2 –1 2 V
Tachometer/Brake
TACH-OUT high level 4.7 5 5.3
-55°C to 125°C, 10 kΩ to 2.5 V V
TACH-OUT low level 0.2
On time 170 220 280 μs
On time change with temp -55°C to 125°C 0.1%
RC-BRAKE input current To 0 V –4.0 –1.9 mA

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ELECTRICAL CHARACTERISTICS (continued)

Unless otherwise stated, these specifications apply over the full temperature range, typical values at TA = 25°C; Pwr VCC =
VCC = 12 V; ROSC = 20 kΩ to VREF; COSC = 2 nF; RTACH = 33 kΩ; CTACH = 10 nF; and all outputs unloaded. TA = TJ.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Threshold to brake, RC-brake 0.8 1.0 1.2
V
Brake hysteresis, RC-brake 0.09 0.4
-55°C to 125°C
SPEED-IN threshold 220 257 290 mV
SPEED-IN input current –30 –5 30 μA
Low-Side Drivers (1)
Voh, –1 mA, down from VCC 1.60 2.50
Voh, –50 mA, down from VCC 1.75 2.45
-55°C to 125°C V
Vol, 1 mA 0.05 0.4
Vol, 50 mA 0.36 0.9
Rise/fall time 10% to 90% slew time, into 1 nF 50 500 ns
High-Side Drivers
Vol, 1 mA 0.1 0.4
-55°C to 125°C V
Vol, 50 mA 1.0 1.8
Leakage current Output voltage = 50 V 30 μA
Fall time 10% to 90% slew time, 50 mA load 50 ns
Oscillator
Frequency -55°C to 125°C 30 80 kHz
Reference
Iref = 0 mA, 25°C 4.85 5.0 5.15
Output voltage V
-55°C to 125°C 4.7 5.0 5.3
Load regulation 0 mA to –20 mA load –40 –5
mV
Line regulation 10 V to 18 V VCC –10 –1 10
Short circuit current -55°C to 125°C 20 100 150 mA
Miscellaneous
Output turn-on delay 1
μs
Output turn-off delay 1

(1) Current available from these pins can peak as high as 0.5 A.

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Block Diagram

QUAD SEL 22
5V
2 VREF
RC-OSC 25 OSC S Q REFERENCE
PWM CLOCK
PWM IN 26 R

E/A OUT 27

E/A IN(+) 1 2.9 V

E/A IN (–) 28
10µA
SSTART 24

ISENSE 3 R Q Q1
ABS VALUE 0.2 V
2.5 V 250 Ω
ISENSE1 4 S
2X
ISENSE2 5 3.1 V

VCC 19
9V
PWM
OV-COAST 23 CLOCK
1.75 V 18 PUA

DIR 6 17 PUB
DIRECTION
SPEED-IN 7 LATCH

0.25 V 16 PUC

+5 V PWM CLOCK
DIR COAST CHOP QUAD 11 PWR VCC

H1 8 D Q H1 CROSS
14 PDA
CONDUCTION
+5 V L PROTECTION
LATCHES

H2 9 D Q H2 DECODER
13 PDB
+5 V L

H3 10 D Q H3

BRAKE 12 PDC
L
EDGE
DETECT 15 GND
+5 V
2k
RC-BRAKE 21 ONE 20 TACH-OUT
SHOT

1V

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DEVICE INFORMATION

Terminal Functions
TERMINAL
DESCRIPTION
NAME NO.
The position decoder logic translates the Hall signals and the DIR signal to the correct driver
signals (PUs and PDs). To prevent output stage damage, the signal on DIR is first loaded
into a direction latch, then shifted through a two-bit register.
As long as SPEED-IN is less than 250 mV, the direction latch is transparent. When
SPEED-IN is higher than 250 mV, the direction latch inhibits all changes indirection.
SPEED-IN can be connected to TACH-OUT through a filter, so that the direction latch is only
transparent when the motor is spinning slowly, and has too little stored energy to damage
power devices.
Additional circuitry detects when the input and output of the direction latch are different, or
DIR, SPEED-IN 6, 7
when the input and output of the shift register are different, and inhibits all output drives
during that time. This can be used to allow the motor to coast to a safe speed before
reversing.
The shift register ensures that direction can not be changed instantaneously. The register is
clocked by the PWM oscillator, so the delay between direction changes is always going to be
between one and two oscillator periods. At 40 kHz, this corresponds to a delay of between
25 μs and 50 μs. Regardless of output stage, 25 μs deadtime should be adequate to ensure
no overlap cross-conduction. Toggling DIR causes an output pulse on TACH-OUT
regardless of motor speed.
E/A IN(+) and E/A IN(–) are not internally committed to allow for a wide variety of uses. They
can be connected to the ISENSE, to TACH-OUT through a filter, to an external command
voltage, to a D/A converter for computer control, or to another op amp for more elegant
feedback loops. The error amplifier is compensated for unity gain stability, so E/A OUT can
be tied to E/A IN(–) for feedback and major loop compensation.
E/A IN(+), E/A IN(–), E/A
1, 28, 27, 26 E/A OUT and PWM In drive the PWM comparator. For voltage-mode PWM systems, PWM In
OUT, PWM IN
can be connected to RC-OSC. The PWM comparator clears the PWM latch, commanding
the outputs to chop.
The error amplifier can be biased off by connecting E/A IN(–) to a higher voltage than /EA
IN(+). When biased off, E/A OUT appears to the application as a resistor to ground. E/A OUT
can then be driven by an external amplifier.
GND 15 All thresholds and outputs are referred to the GND pin except for the PD and PU outputs.
The three shaft position sensor inputs consist of hysteresis comparators with input pullup
resistors. Logic thresholds meet TTL specifications and can be driven by 5-V CMOS, 12-V
CMOS, NMOS, or open-collectors.
Connect these inputs to motor shaft position sensors that are positioned 120 electrical
degrees apart. If noisy signals are expected, zener clamp and filter these inputs with 6-V
H1, H2, H3 8, 9, 10
zeners and an RC filter. Suggested filtering components are 1 kΩ and 2 nF. Edge skew in
the filter is not a problem, because sensors normally generate modified gray code with only
one output changing at a time, but rise and fall times must be shorter than 20 μs for correct
tachometer operation. Motors with 60 electrical degree position sensor coding can be used if
one or two of the position sensor signals is inverted.
The current sense amplifier has a fixed gain of approximately two. It also has a built-in level
shift of approximately 2.5 V. The signal appearing on ISENSE is:
ISENSE = 2.5 V + (2 × ABS ( ISENSE1 – ISENSE2) )
ISENSE1 and ISENSE2 are interchangeable and can be used as differential inputs. The
differential signal applied can be as high as ±0.5 V before saturation.
If spikes are expected on ISENSE1 or ISENSE2, they are best filtered by a capacitor from
ISENSE to ground. Filtering this way allows fast signal inversions to be correctly processed
ISENSE1, ISENSE2, by the absolute value circuit. The peak-current comparator allows the PWM to enter a
3, 4, 5
ISENSE current-limit mode with current in the windings never exceeding approximately 0.2 V /
RSENSE. The overcurrent comparator provides a fail-safe shutdown in the unlikely case of
current exceeding 0.3 V / RSENSE. Then, softstart is commanded, and all outputs are turned
off until the high current condition is removed. It is often essential to use some filter driving
ISENSE1 and ISENSE2 to reject extreme spikes and to control slew rate. Reasonable
starting values for filter components might be 250-Ω series resistors and a 5-nF capacitor
between ISENSE1 and ISENSE2. Input resistors should be kept small and matched to
maintain gain accuracy.
This input can be used as an over-voltage shut-down input, as a coast input, or both. This
OV-COAST 23
input can be driven by TTL, 5-V CMOS, or 12-V CMOS.

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Terminal Functions (continued)

TERMINAL
DESCRIPTION
NAME NO.
These outputs can drive the gates of N-channel power MOSFETs directly or they can drive
the bases of power Darlingtons if some form of current limiting is used. They are meant to
drive low-side power devices in high-current output stages. Current available from these pins
PDA, PDB, PDC 12, 13, 14
can peak as high as 0.5 A. These outputs feature a true totem-pole output stage. Beware of
exceeding device power dissipation limits when using these outputs for high continuous
currents. These outputs pull high to turn a “low-side” device on (active high).
These outputs are open-collector, high-voltage drivers that are meant to drive high-side
power devices in high-current output stages. These are active low outputs, meaning that
these outputs pull low to command a high-side device on. These outputs can drive
PUA, PUB, PUC 16, 17, 18 low-voltage PNP Darlingtons and P-channel MOSFETs directly, and can drive any
high-voltage device using external charge pump techniques, transformer signal coupling,
cascode level-shift transistors, or opto-isolated drive (high-speed opto devices are
recommended). (See applications).
This supply pin carries the current sourced by the PD outputs. When connecting PD outputs
directly to the bases of power Darlingtons, the PWR VCC pin can be current limited with a
PWR VCC 11
resistor. Darlington outputs can also be "Baker Clamped" with diodes from collectors back to
PWR VCC. (See Applications)
The device can chop power devices in either of two modes, referred to as “two-quadrant”
(Quad Sellow) and “four quadrant” (Quad Sel high). When two-quadrant chopping, the
pulldown power devices are chopped by the output of the PWM latch while the pullup drivers
remain on. The load chops into one commutation diode, and except for back-EMF, will
exhibit slow discharge current and faster charge current. Two-quadrant chopping can be
QUAD SEL 22 more efficient than four-quadrant.
When four-quadrant chopping, all power drivers are chopped by the PWM latch, causing the
load current to flow into two diodes during chopping. This mode exhibits better control of load
current when current is low, and is preferred in servo systems for equal control over
acceleration and deceleration. The QUAD SEL input has no effect on operation during
braking.
Each time the TACH-OUT pulses, the capacitor tied to RC-BRAKE discharges from
approximately 3.33 V down to 1.67 V through a resistor. The tachometer pulse width is
approximately T = 0.67 RT CT, where RT and CT are a resistor and capacitor from
RC-BRAKE to ground. Recommended values for RT are 10 kΩ to 500 kΩ, and
recommended values for CT are 1 nF to 100 nF, allowing times between 5 μs and 10 ms.
Best accuracy and stability are achieved with values in the centers of those ranges.
RC-BRAKE also has another function. If RC-BRAKE pin is pulled below the brake threshold,
RC-BRAKE 21 the device enters brake mode. This mode consists of turning off all three high-side devices,
enabling all three low-side devices, and disabling the tachometer. The only things that inhibit
low-side device operation in braking are low-supply, exceeding peak current, OV-COAST
command, and the PWM comparator signal. The last of these means that if current sense is
implemented such that the signal in the current sense amplifier is proportional to braking
current, the low-side devices will brake the motor with current control. (See applications)
Simpler current sense connections results in uncontrolled braking and potential damage to
the power devices.
The UC1625 can regulate motor current using fixed-frequency pulse width modulation
(PWM). The RC-OSC pin sets oscillator frequency by means of timing resistor ROSC from the
RC-OSC pin to VREF and capacitor COSC from RC-OSC to Gnd. Resistors 10 kΩ to 100 kΩ
and capacitors 1 nF to 100 nF works the best, but frequency should always be below 500
kHz. Oscillator frequency is approximately:
F = 2/(ROSC x COSC )
RC-OSC 25
Additional components can be added to this device to cause it to operate as a fixed off-time
PWM rather than a fixed frequency PWM, using the RC-OSC pin to select the monostable
time constant.
The voltage on the RC-OSC pin is normally a ramp of about 1.2 V peak-to-peak, centered at
approximately 1.6 V. This ramp can be used for voltage-mode PWM control, or can be used
for slope compensation in current-mode control.

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Terminal Functions (continued)

TERMINAL
DESCRIPTION
NAME NO.
Any time that VCC drops below threshold or the sensed current exceeds the over-current
threshold, the soft-start latch is set. When set, it turns on a transistor that pulls down on
SSTART. Normally, a capacitor is connected to this pin, and the transistor will completely
discharge the capacitor. A comparator senses when the NPN transistor has completely
discharged the capacitor, and allows the soft-start latch to clear when the fault is removed.
When the fault is removed, the soft-start capacitor charges from the on-chip current source.
SSTART clamps the output of the error amplifier, not allowing the error amplifier output
SSTART 24
voltage to exceed SSTART regardless of input. The ramp on RC-OSC can be applied to
PWM In and compared to E/A OUT. With SSTART discharged below 0.2 V and the ramp
minimum being approximately 1.0 V, the PWM comparator keeps the PWM latch cleared and
the outputs off. As SSTART rises, the PWM comparator begins to duty-cycle modulate the
PWM latch until the error amplifier inputs overcome the clamp. This provides for a safe and
orderly motor start-up from an off or fault condition. A 51-kΩ resister is added between VREF
and SSTART to ensure switching.
Any change in the H1, H2, or H3 inputs loads data from these inputs into the position sensor
latches. At the same time data is loaded, a fixed-width 5-V pulse is triggered on TACH-OUT.
The average value of the voltage on TACH-OUT is directly proportional to speed, so this
output can be used as a true tachometer for speed feedback with an external filter or
TACH-OUT 20 averaging circuit which usually consists of a resistor and capacitor.
Whenever TACH-OUT is high, the position latches are inhibited, such that during the noisiest
part of the commutation cycle, additional commutations are not possible. Although this
effectively sets a maximum rotational speed, the maximum speed can be set above the
highest expected speed, preventing false commutation and chatter.
This device operates with supplies between 10 V and 18 V. Under-voltage lockout keeps all
outputs off below 7.5 V, insuring that the output transistors never turn on until full drive
VCC 19 capability is available. Bypass VCC to ground with an 0.1-μF ceramic capacitor. Using a
10-μF electrolytic bypass capacitor as well can be beneficial in applications with high supply
impedance.
This pin provides regulated 5 V for driving Hall-effect devices and speed control circuitry.
VREF reaches 5 V before VCC enables, ensuring that Hall-effect devices powered from
VREF 2
VREF becomes active before the UC1625 drives any output. For proper performance VREF
should be bypassed with at least a 0.1-μF capacitor to ground.
TYPICAL CHARACTERISTICS
Oscillator Frequency Tachometer on Time
vs vs
COSC and ROSC RT and CT
1 MHz 100 ms

10 ms RT – 500 k
ROSC – 10 k RT – 100 k
100 kHz
Oscillator Frequency

ROSC – 10 k
1 ms
On Time

ROSC – 100 k
10 kHz
100 ms

RT – 10 k
1 kHz 10 ms RT – 30 k

1 ms
100 Hz 0.001 0.01 0.1
0.001 0.01 0.1 CT – mF
COSC (mF)
Figure 2. Figure 3.

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TYPICAL CHARACTERISTICS (continued)

Supply Current Soft-Start Pullup Current
vs vs
Temperature Temperature
20 -5

18 -6

16 -7

14 -8

Soft Start Current – mA

Supply Current – mA

12 -9

10 -10

8 -11

6 -12

4 -13

2 -14

0 -15
-75 -50 -25 0 25 50 75 100 125 -75 -50 -25 0 25 50 75 100 125

Temperature – C Temperature – C
Figure 4. Figure 5.

Soft-Start Discharge Current Current Sense Amplifier Transfer Function

vs vs
Temperature ISENSE2 – ISENSE1
1.25 3.5

1.00
Soft Start Current – mA

.75
ISENSE – V

.50

.25

0 2.5
-75 -50 -25 0 25 50 75 100 125 -0.5 0.0 0.5
Temperature – C
ISENSE2 – ISENSE1 – V
Figure 6. Figure 7.

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APPLICATION INFORMATION

Cross Conduction Prevention

The UC1625 inserts delays to prevent cross conduction due to overlapping drive signals. However, some thought
must always be given to cross conduction in output stage design because no amount of dead time can prevent
fast slewing signals from coupling drive to a power device through a parasitic capacitance.
The UC1625 contains input latches that serve as noise blanking filters. These latches remain transparent through
any phase of a motor rotation and latch immediately after an input transition is detected. They remain latched for
two cycles of the PWM oscillator. At a PWM oscillator speed of 20 kHz, this corresponds to 50 μs to 100 μs of
blank time which limits maximum rotational speed to 100 kRPM for a motor with six transitions per rotation or 50
kRPM for a motor with 12 transitions per rotation.
This prevents noise generated in the first 50 μs of a transition from propagating to the output transistors and
causing cross-conduction or chatter.
The UC1625 also contains six flip flops corresponding to the six output drive signals. One of these flip flops is set
every time that an output drive signal is turned on, and cleared two PWM oscillator cycles after that drive signal
is turned off. The output of each flip flop is used to inhibit drive to the opposing output (Figure 8). In this way, it is
impossible to turn on driver PUA and PDA at the same time. It is also impossible for one of these drivers to turn
on without the other driver having been off for at least two PWM oscillator clocks.

EDGE SHIFT
S Q
FINDER REG

PWM R Q PUA
CLK
PULL UP

FROM S Q
DECODER
R Q
PULL PDA
DOWN

Figure 8. Cross Conduction Prevention

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Power Stage Design

The UC1625 is useful in a wide variety of applications, including high-power in robotics and machinery. The
power output stages used in such equipment can take a number of forms, according to the intended performance
and purpose of the system. Figure 9 show four different power stages with the advantages and disadvantages of
each.
For high-frequency chopping, fast recovery circulating diodes are essential. Six are required to clamp the
windings. These diodes should have a continuous current rating at least equal to the operating motor current,
since diode conduction duty-cycle can be high. For low-voltage systems, Schottky diodes are preferred. In higher
voltage systems, diodes such as Microsemi UHVP high voltage platinum rectifiers are recommended.
In a pulse-by-pulse current control arrangement, current sensing is done by resistor RS, through which the
transistor's currents are passed (Fig. A, B, and C). In these cases, RD is not needed. The low-side circulating
diodes go to ground and the current sense terminals of the UC1625 (ISENSE1 and ISENSE2) are connected to RS
through a differential RC filter. The input bias current of the current sense amplifier causes a common mode
offset voltage to appear at both inputs, so for best accuracy, keep the filter resistors below 2 kΩ and matched.
The current that flows through RS is discontinuous because of chopping. It flows during the on time of the power
stage and is zero during the off time. Consequently, the voltage across RS consists of a series of pulses,
occurring at the PWM frequency, with a peak value indicative of the peak motor current.
To sense average motor current instead of peak current, add another current sense resistor (RD in Fig. D) to
measure current in the low-side circulating diodes, and operate in four quadrant mode (pin 22 high). The
negative voltage across RD is corrected by the absolute value current sense amplifier. Within the limitations
imposed by Table 2, the circuit of Fig. B can also sense average current.

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FIGURE A FIGURE B

TO TO
MOTOR MOTOR

RS RS

FIGURE C
FIGURE D

TO
TO
MOTOR
MOTOR

RS RD
RS

Figure 9. Four Power Stage Designs

Table 2. Imposed Limitations for Figure 9

SAFE CURRENT SENSE
2 QUADRANT 4 QUADRANT POWER REVERSE
BRAKING Pulse-by-Pulse Average
Figure A Yes No No N0 Yes No
Figure B Yes Yes No In 4-quad mode only Yes Yes
Figure C Yes Yes Yes In 4-quad mode only Yes No
Figure D Yes Yes Yes In 4-quad mode only Yes Yes

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For drives where speed is critical, P-channel MOSFETs can be driven by emitter followers as shown in
Figure 10. Here, both the level shift NPN and the PNP must withstand high voltages. A zener diode is used to
limit gate-source voltage on the MOSFET. A series gate resistor is not necessary, but always advisable to control
overshoot and ringing.
High-voltage optocouplers can quickly drive high-voltage MOSFETs if a boost supply of at least 10 V greater
than the motor supply is provided (See Figure 11) To protect the MOSFET, the boost supply should not be
higher than 18 V above the motor supply.
For under 200-V 2-quadrant applications, a power NPN driven by a small P-Channel MOSFET performs well as
a high-side driver as in Figure 12. A high voltage small-signal NPN is used as a level shift and a high voltage
low-current MOSFET provides drive. Although the NPN does not saturate if used within its limitations, the
base-emitter resistor on the NPN is still the speed-limiting component.
Figure 13 shows a power NPN Darlington drive technique using a clamp to prevent deep saturation. By limiting
saturation of the power device, excessive base drive is minimized and turn-off time is kept fairly short. Lack of
base series resistance also adds to the speed of this approach.

Figure 10. Fast High-Side P-Channel Driver Figure 11. Optocoupled N-Channel High-Side
Driver

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Figure 12. Power NPN High-Side Driver Figure 13. Power NPN Low-Side Driver

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Fast High-Side N-Channel Driver with Transformer Isolation

A small pulse transformer can provide excellent isolation between the UC1625 and a high-voltage N-Channel
MOSFET while also coupling gate drive power. In this circuit (shown in Figure 14), a UC3724 is used as a
transformer driver/encoder that duty-cycle modulates the transformer with a 150-kHz pulse train. The UC3725
rectifies this pulse train for gate drive power, demodulates the signal, and drives the gate with over 2-A peak
current.

+12V VMOTOR
3
33kW 6 7
PUA 2
7 UC3724N UC3725N
4
4 8
1:2
8 1 2 5 1 6 3

5kW 1nF 100nF

TO MOTOR

Figure 14. Fast High-Side N-Channel Driver with Transformer Isolation

Both the UC3724 and the UC3725 can operate up to 500 kHz if the pulse transformer is selected appropriately.
To raise the operating frequency, either lower the timing resistor of the UC3724 (1 kΩ min), lower the timing
capacitor of the UC3724 (500 pF min) or both.
If there is significant capacitance between transformer primary and secondary, together with very high output
slew rate, then it may be necessary to add clamp diodes from the transformer primary to 12 V and ground.
General purpose small signal switching diodes such as 1N4148 are normally adequate.
The UC3725 also has provisions for MOSFET current limiting. See the UC3725 data sheet for more information
on implementing this.

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Computational Truth Table

Table 3 shows the outputs of the gate drive and open collector outputs for given hall input codes and direction
signals. Numbers at the top of the columns are pin numbers.
These devices operate with position sensor encoding that has either one or two signals high at a time, never all
low or all high. This coding is sometimes referred to as "120° Coding" because the coding is the same as coding
with position sensors spaced 120 magnetic degrees about the rotor. In response to these position sense signals,
only one low-side driver turns on (go high) and one high-side driver turns on (pull low) at any time.

Table 3. Computational Truth Table

INPUTS OUTPUTS
DIR H1 H2 H3 Low-Side High-Side
6 8 9 10 12 13 14 16 17 18
1 0 0 1 L H L L H H
1 0 1 1 L L H L H H
1 0 1 0 L L H H L H
1 1 1 0 H L L H L H
1 1 0 0 H L L H H L
1 1 0 1 L H L H H L
0 1 0 1 L L H H L H
0 1 0 0 L L H L H H
0 1 1 0 L H L L H H
0 0 1 0 L H L H H L
0 0 1 1 H L L H H L
0 0 0 1 H L L H L H
X 1 1 1 L L L H H H
X 0 0 0 L L L H H H

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+5V TO HALL +15V VMOTOR

VREF
SENSORS

3kW +
100nF 100nF + 100mF
2N3904
20mF
20mF 10W
10kW
3kW 10kW
ROSC 2 19 11
QUAD 33kW 2N3906
IRF9350
22 3kW
DIR
16
6 TO
1k 17 MOTOR
1 TO OTHER
CHANNELS
18
28 UC3625
UC1625
4kW
100nF 14 REQUIRED
27 TO OTHER FOR BRAKE
CHANNELS AND FAST
13
25 10W REVERSE
2200pF IRF532
12
COSC
15 20

BRAKE 21 26 3 24 23 8 9 10 4 5 7 10kW

5nF 100nF
3nF 68kW REQUIRED
CT RT FROM 240W FOR
100nF HALL AVERAGE
2nF SENSORS 0.02 CURRENT
5nF 240W W SENSING
51kW 2nF RS
0.02
2nF W
RD
VREF

Figure 15. 45-V/8-A Brushless DC Motor Drive Circuit

N-Channel power MOSFETs are used for low-side drivers, while P-Channel power MOSFETs are shown for
high-side drivers. Resistors are used to level shift the UC1625 open-collector outputs, driving emitter followers
into the MOSFET gate. A 12-V zener clamp insures that the MOSFET gate-source voltage never exceeds 12 V.
Series 10-Ω gate resistors tame gate reactance, preventing oscillations and minimizing ringing.
The oscillator timing capacitor should be placed close to pins 15 and 25, to keep ground current out of the
capacitor. Ground current in the timing capacitor causes oscillator distortion and slaving to the commutation
signal.
The potentiometer connected to pin 1 controls PWM duty cycle directly, implementing a crude form of speed
control. This control is often referred to as "voltage mode" because the potentiometer position sets the average
motor voltage. This controls speed because steady-state motor speed is closely related to applied voltage.
Pin 20 (Tach-Out) is connected to pin 7 (SPEED IN) through an RC filter, preventing direction reversal while the
motor is spinning quickly. In two-quadrant operation, this reversal can cause kinetic energy from the motor to be
forced into the power MOSFETs.
A diode in series with the low-side MOSFETs facilitates PWM current control during braking by insuring that
braking current will not flow backwards through low-side MOSFETs. Dual current-sense resistors give continuous
current sense, whether braking or running in four-quadrant operation, an unnecessary luxury for two-quadrant
operation.
The 68-kΩ and 3-nF tachometer components set maximum commutation time at 140 μs. This permits smooth
operation up to 35,000 RPM for four-pole motors, yet gives 140 μs of noise blanking after commutation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 2-Dec-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-9168902VYA ACTIVE CDIP SB JDJ 28 12 Non-RoHS Call TI N / A for Pkg Type -55 to 125 5962-9168902VY Samples
& Green A
UC1625-SP

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Dec-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-9168902VYA JDJ CDIP SB 28 12 506.98 15.24 13440 NA

Pack Materials-Page 1
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