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    ECE465 Lecture Notes # 11 Clocking Methodologies: Shantanu Dutt UIC

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    Mohammed El-Adawy
    1) Synchronous sequential circuits require all state transitions to occur on a single edge of the clock and only one transition per clock period. 2) Clock skew, the difference in clock arrival times between flip-flops, must be minimized and accounted for in determining the minimum clock period. 3) Race conditions can occur if a flip-flop output changes state more than once per clock period, which is avoided through proper clocking techniques like edge-triggered flip-flops or two-phase clocking.

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    ECE465 Lecture Notes # 11 Clocking Methodologies: Shantanu Dutt UIC

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    Mohammed El-Adawy
    77 views21 pages
    1) Synchronous sequential circuits require all state transitions to occur on a single edge of the clock and only one transition per clock period. 2) Clock skew, the difference in clock arrival times between flip-flops, must be minimized and accounted for in determining the minimum clock period. 3) Race conditions can occur if a flip-flop output changes state more than once per clock period, which is avoided through proper clocking techniques like edge-triggered flip-flops or two-phase clocking.

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    Lect10 Clocking Short

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    1) Synchronous sequential circuits require all state transitions to occur on a single edge of the clock and only one transition per clock period. 2) Clock skew, the difference in clock arrival times between flip-flops, must be minimized and accounted for in determining the minimum clock period. 3) Race conditions can occur if a flip-flop output changes state more than once per clock period, which is avoided through proper clocking techniques like edge-triggered flip-flops or two-phase clocking.

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    77 views21 pages

    ECE465 Lecture Notes # 11 Clocking Methodologies: Shantanu Dutt UIC

    Uploaded by

    Mohammed El-Adawy
    1) Synchronous sequential circuits require all state transitions to occur on a single edge of the clock and only one transition per clock period. 2) Clock skew, the difference in clock arrival times between flip-flops, must be minimized and accounted for in determining the minimum clock period. 3) Race conditions can occur if a flip-flop output changes state more than once per clock period, which is avoided through proper clocking techniques like edge-triggered flip-flops or two-phase clocking.

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    ECE465 Lecture Notes # 11 Clocking Methodologies

    Shantanu Dutt UIC

    Acknowledgement: (1) Most slides prepared by Huan Ren from Prof. Dutts Lecture Notes (some modifications made by Prof. Dutt); (2) Some slides extracted from Prof. David Pans (UT Austin) slides as indicated

    Timing Methodologies
    Synchronous Sequential Circuits
    External I/P Comb. Logic Memory Clk External O/P TOPP,Logic
    (critical path delay In the o/p logic part)

    00,11/0 A

    01/1

    TNSP,Logic
    (critical path delay In the NS logic part)

    00,01,10/0 B 01/0 11/0 11/0 C 10,00/1 Transition occurs only on positive edge of Clk

    Features Required for Correct Operation


    1) All State Transitions take place only with respect to a particular event in the clock (e.g., positive or negative edge, etc. )

    Timing Methodologies (contd)


    Features Required for Correct Operation
    2) Only one state transition should take place in one clock period. 3) All inputs to all FFs/latches should be correctly available with appropriate setup time (Tsetup or Tsu) and hold time (Thold or Th) around the triggering edge of the clock. Tsetup Thold

    Input Clock Tperiod =TClk ith state transition (i+1)th state (i+2)th state transition transition [could be to the same state] (i+3)th state transition

    Clock Routing
    A path from the clock source to clock sinks (FFs) Different FFs are at different distances from the clock source

    Clock Source

    FF

    FF

    FF

    FF

    FF

    FF

    FF

    FF

    FF

    FF

    This leads to the clock ariving at different FFs at slightly different time. This difference in clock arrival times is called clock skew
    From: David Pan, UT Austin

    Timing Methodologies: Clock Skew Problem


    Real-world problems that can cause the three requirements to be violated
    A) Clock Skew: Max(arrival time difference of the same clock edge betw all FF pairs).
    2 1

    Safe: If blue horse wins race & wins it by a margin of at least Th

    Unsafe: If brown horse wins race

    Tskew

    IN

    1 D1

    D Q FF1 Q1 Clk1

    0 1

    Logic

    0 D2

    0 D Q FF2 Q2 Clk2

    Clk1

    Clk

    2 Values before the clock +ve edge

    Clk2

    New value of D2 D1 Current overwrites old value state 00 10 before Q2 changes D2 Correct Incorrect transition transition This causes an incorrect Q1 11 Q2 change when +ve Q2 edge arrives at Clk2

    IN 1 Tskew= max (|difference between clock pulses (rising edges) of clock D1 inputs of any two FFs in the system|)
    Tsu Clk1 D1 Typical or min TPLH Th Clk

    Safe Value of Tskew


    D Q FF1 Q1 Clk1

    Logic

    0
    D2

    0 D Q FF2 Q2
    Clk2

    Safe if: min (TPLH of FF)+min (TP,Logic between Q1 & Q2)>Tskew+Th i.e. if: Tskew < min (TPLH)+min (TP,Logic)-Th Similarly for 1 to 0 transition of Q1: TPHL comes into play, then safe if: Tskew < min (TPHL)+min (TP,Logic)-Th

    Q1

    D2 Clk2 Tskew

    min TP,Logic

    Th

    Thus we need: Tskew < min (min TPLH, min TPHL)+min (TNSP,Logic) Th = min(TP,FF) + min(TNS P,Logic) Th, where TNSP,Logic is the prop. delay of the next state (NS) logic portion of the entire comb. logic in the system. Thus, the safe Tskew limit is based on minimum propagation delay of FFs and the NS logic

    Determining Clock Period: Edge Triggered System


    TOPP,Logic Level sens. latch Positive edge trigg. Clk Comb. Logic FF1 Clk1 FF2 Clk2 TNSP,Logic Memory of FF bank with delay TP,FF

    negative edge trigg. Clk Tsu T skew TP,FF TP,Logic


    Clk1 Clk2 TClk

    Clk Max(typical TPHLand typical TPLH

    TClk-Tskew > max(TP,FF)+ max(TNSP,Logic)+Tsetup = TP,FF+ TNSP,Logic+Tsetup


    i.e., we will use the normal convention of using TP,FF to mean max(TP,FF) TNSP,Logic to mean max(TNSP,Logic) Also, TClk-Tskew > TP,FF+ TOPP,Logic, where TOPP,Logic is the output logic portion of combinational logic.

    Determining the Clock Period (Contd.)


    TP,FF + TNSP,Logic + Tsetup, AND
    TP,FF + TOPP,Logic

    Clk1

    If with skew

    TClk

    TClk> Tskew+ TP,FF+ TNSP,Logic +Tsetup AND TClk> Tskew+ TP,FF+ TOPP,Logic Thus TClk> max(Tskew+ TP,FF+ TNSP,Logic +Tsetup, Tskew+ TP,FF+ TOPP,Logic)

    Use 10% buffer for safety


    TClk=1.1max(Tskew+ TP,FF+ TNSP,Logic +Tsetup, Tskew+ TP,FF+ TOPP,Logic) Tskew= max (|difference between clock pulses (rising edges) of clock inputs of any two FFs in the system|)

    Clock Skew
    Clock skew is the maximum difference in the arrival time of a clock signal at two different components. Clock skew forces designers to use a large time period between clock pulses. This makes the system slower. So, in addition to other objectives, clock skew should be minimized during clock routing.

    From: David Pan, UT Austin

    Clock Design Problem


    What are the main concerns for clock design? Skew
    No. 1 concern for clock networks For increased clock frequency, skew may contribute over 10% of the system cycle time very important, as clock is a major power consumer! It switches at every clock cycle! Clock is often a very strong aggressor May need shielding Not really important But slew rate is important (sharp transition)
    From: David Pan, UT Austin

    Power

    Noise

    Delay

    The Clock Routing Problem


    Given a source and n sinks (FFs). Connect all sinks to the source by an interconnect tree so as to minimize:
    Clock Skew = maxi,j |ti - tj| Delay = maxi ti Total wirelength Noise and coupling effect

    From: David Pan, UT Austin

    H-Tree Clock Routing


    Tapping Point 4 Points 16 Points

    From: David Pan, UT Austin

    Method of Means and Medians (MMM)


    Applicable when the clock terminals are arbitrarily arranged. Follows a strategy very similar to H-Tree. Recursively partition the terminals into two sets of equal size (median). Then, connect the center of mass of the whole circuit to the centers of mass of the two sub-circuits (mean). Clock skew is only minimized heuristically. The resulting tree may not have zero-skew.

    From: David Pan, UT Austin

    An Example of MMM

    centers of mass

    From: David Pan, UT Austin

    Another Problem: Race ConditionReason 1


    A race condition occurs when a FF/latch output changes more than once in a clock cycle (cc). This happens when after the O/P of a latch changes, it feeds back to its input via some logic when the latch is still enabled in the same cc. This cause the O/P to change again. Tsu

    Clk
    D

    Other I/Ps Comb. Logic Q D latch Clk 2 changes of state in Q in 1 cc D

    Race Condition: Reason 1 (contd)


    Race condition is generally a problem with level sensitive latches. Can be solved using: Other I/Ps a) Edge-triggered FFs. Comb. Clk Logic
    D Q Only 1 O/P change per cc. Q D FF D Clk

    b) Narrow-width clocking. TClk T >T +T


    Clk skew

    Other I/Ps

    TP,Logic+Tsetup Tw<min (TP,FF)+min(TP,Logic)

    P,FF+

    Comb. Logic
    Q D latch D
    Narrow Width Clk

    Tw

    min (min TPLH, min

    Correct State Transition Using Level-Sensitive Latches


    0/1

    Transition for the darkened arrow:


    1
    Comb. Logic 1 1
    CS

    0/0 00

    10 1/1 1/0 1/0 0/0 11

    1
    NS

    2 level sens. latches

    0
    Clk

    Comb. Logic 1 0 0 Clk 1

    1/1 0/1

    01

    Comb. Logic 0 0 1 Clk 1

    Race Condition: Reason 2


    (Unequal logic delay for different NS bits) Incorrect State Transition Using Level-Sensitive Latches
    Required transition for the darkened arrow becomes incorrect transition corresponding to the dashed arrow
    1 Comb. Logic 1 1 slow 0 Clk 1 Comb. Logic 1 1 0 Clk 0 1 fast 0 1 Comb. Logic 1 1 1 Clk 1 0 1 1 0/1 0/0 00 10 1/1

    1/0
    1/1 0/1 01

    1/0

    11
    0/0

    Comb. Logic 1 0 1 0

    Clk

    Comb. Logic 0 0 0 Clk 0

    0 2 level-sens. latches

    No Race Condition Using Edge-Triggered FFs


    0/1

    Correct transition for the darkened arrow irrespective of the relative speed of different excitation (next state) outputs
    1 Comb. Logic 1 1 slow 0 Clk 1 Comb. Logic 1 1 0 Clk 0 1 fast 0 1 Comb. Logic 1 1 0 Clk 1 0 1

    0/0 00

    10 1/1 1/0 11 0/0

    1/1 0/1 Comb. Logic 1 0 0 1 0

    1/0

    01

    Clk

    Comb. Logic 0 0 1

    0 2 M-S or edge- Period Between State 1 triggered FFs Transitions (also clock period) Clk

    Generally, Cost(master-slave (MS) LS latches) < Cost(edge-trigg. FF)


    Correct transition for the darkened arrow irrespective of the relative speed of different excitation (next state) outputs
    1 Comb. Logic 1 0 Clk2 Clk1 Clk2 1 0 0 1 Comb. Logic 1 0 0 1

    No Race Condition Using 2-phase clocking and MS level sensitive latches


    0/1 0/0 00 1/0 01 Comb. Logic 1 0 0 1 10 1/1 11 0/0 Comb. Logic 0 1 Clk2 Clk1 0 1 0

    1/0

    1 slow 1 fast

    Clk2 Clk1

    0 slow 1 fast

    Clk2 Clk1

    Clk1 T2-1

    Tgap T1-2

    Two-phase clock period determination


    I/Ps Comb. Logic O/Ps

    CS

    NS

    TClk

    Clk2

    (1-a)T1-2 aT1-2

    Clk2 Clk1 Tgap1>Tskew (to avoid overlap and thus a race condition) T2-1+aT1-2(assuming 0 Tgap1, 0< a <1) > TP,FF+TP,Logic+Tsu
    (Note: Introducing a Tgap1 of at least Tskew also takes care of the reqmt to allow for Tskew in the above sum of the 3 delay components)

    Tgap2 Clk1 T2-1 T gap1 T1-2

    T1-2 = T2-1 (for symmetry requirements)

    (1- a)T1-2 + Tgap2 > TP,FF + Tsu + Tskew Tgap1 = Tgap2 (for symmetry requirements) Tclk = 1.1(T2-1 + T1-2 + Tgap1 + Tgap2 ) = 1.1(2TP,FF+TP,Logic+2Tsu+2Tskew) [w/ 10% safety gap]

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