Sr. No. Name of The I/O Direction Width Description 1 2 3

Sr.
Name of the Direction Width Description

No. I/O
1 a Input 8 Dividend Input (Operand 1)
2 b Input 4 Divisor Input (Operand 2)
3 Start Input 1 Start Division operation (when 1, the
shift and subtraction operations take
place at each clock edge. Also, Rst must
be 0.)
4 Rst Input 1 Reset Input (when 1, the output Op is
00000000 and ready_out is 0)
5 Clk Input 1 Clock Input
6 rem Output 4 Remainder Output
qu 8 Quotient Output
7 Ready_out Output 1 After the division operation is
complete, its value is 1.
Example
1001 0001 =a
1010 =b
Temporary memory t = 00000000

Clock 1: left shift {t,a}; compare t with b; // here t = 0000 0001, a = 001 0001 X
As t < b, qu[7]=0

Clock 2: left shift {t,a}; compare t with b; // here t = 0000 0010, a = 01 0001 XX
As t < b, qu[6]=0

Clock 3: left shift {t,a}; compare t with b; // here t = 0000 0101, a = 1 0001 XXX
As t < b, qu[5]=0

Clock 4: left shift {t,a}; compare t with b; // here t = 0000 1001, a = 0001 XXXX
As t < b, qu[4]=0
Example
1001 0001 =a
1010 =b
Clock 5: left shift {t,a}; compare t with b; // here t = 0001 0010, a = 001 XXXXX
As t > b, qu[3]=1; t = t-b // t= 0000 1000

Clock 6: left shift {t,a}; compare t with b; // here t = 0001 0000, a = 01 XXXXXX
As t > b, qu[2]=1; t = t-b // t= 0000 0110

Clock 7: left shift {t,a}; compare t with b; // here t = 0000 1100, a = 1 XXXXXXX
As t > b, qu[1]=1; t = t-b // t= 0000 0010

Clock 8: left shift {t,a}; compare t with b; // here t = 0000 0101, a = XXXXXXXX
As t < b, qu[0]=0;
Ready_out =1; rem = t;
Seq Divider
output reg [7:0] qu;
always @(posedge clk)
output reg ready_out; begin
input [7:0] a; if (rst)
input [3:0] b; begin
input clk,rst; rem=4'b0000;
output reg [3:0] rem; ready_out=1'b0;
count=0;
tmp = {8'b00000000,a};
reg [3:0] count; tmp0 = 8'b00000000;
reg [15:0] tmp; qu =8'b11111111;
reg [7:0] tmp0; end
Seq Divdider
else if (count < 8)

begin
if (~rst) count = count +1;
tmp = tmp << 1;
if (count == 8) begin rem = tmp0;
tmp0 = tmp[15:8];
ready_out = 1'b1; end
if (tmp0 > b)
begin
end
qu[7-count] = 1;
tmp0 = tmp0-b;
tmp[15:8]= tmp0;
end
endmodule
else
qu[7-count] = 0;
end
Seq Divider: TB
initial begin
// Initialize Inputs
a = 54;
b = 7;
clk = 0;
rst = 0;
#5
rst = 1;
#20
rst = 0;
end
// Wait 100 ns for global reset to finish
always #10 clk=~clk;
Loop
module looopadd(
input [3:0] a,
input [3:0] b,
for (i=0; i <=3; i=i+1)
output reg[3:0] c
begin
); c[i] = a[i] + b[i];
integer i; end
always @(a or b) end
begin
endmodule
Shift Register with parallel load
1. Design an 8-Bit register circuit with the following specifications.—PARALLEL LOAD and
Left SHIFTER
a. If input line parallelload is high, the register loads the value from input bus
parallelinput.
b. If the parallelload is low,
The value in (i-1) th Bit of the register is loaded into the ith Bit of the register
for i=1 to i=7. The value in the input line Seq-In is loaded into the 0th Bit of
the register and value in the 7th Bit of the register is sent as output from
line Seq-Out.
c. Step a is repeated at each edge of the clock.
parallelload
7 6 5 4 3 2 1 0
Seq-In
8 Bit Register (Memory)
Clock
8 Bit input
parallelinput
Seq-Out
• Shift Register with parallel load
module parallelload1(
always @(posedge clk)
input clk, begin
input parallelload, if (parallelload)
input [7:0] input1, tmp <= input1;
input sin, else
output sout begin
tmp = {tmp[6:0], sin};
);
end
end
assign sout = tmp[7];
reg [7:0] tmp; endmodule
Test Bench for Shift Register Parallel Load
initial begin
forever begin #10
clk <= 0; parallelload = 0;
#5 end
clk <= 1;
#5
clk <= 0; initial begin
end forever begin
end sin = 0;
#7
initial begin
sin = 0;
parallelload = 0; #8
#10 sin = 0;
input1=8'b11111111; end
#10 end
parallelload = 1;
1. Design of traffic light controller with the following specifications.

 The controller is to be designed for a traffic light to be positioned at an intersection
between a north-south and an east-west street.
 The traffic moves in north-south or east-west, direction only. There is no
perpendicular movement.
 On the reset signal, system will enter into the configuration –North-South GREEN
and East-West RED.
 After a delay of 15 units of time the next configuration –North-South YELLOW and
East-West YELLOW.
 Table below, illustrates all the configurations and delays.
 From configuration 6, the controller moves to configuration 1.
Traffic North East Delay
Light South West
sequenc
es
1 Green Red 15
2 Yellow Red 3
N o r th 3 Red Red 1
4 Red Green 15
W est E ast 5 Red Yellow 3
6 Red Red 1
S o u th
Delay 15 Delay 3 Delay 1
So S1 S2 S3
000 001 010 100
Output 100001 Output 100010 Output 100100 Output 001100;
Delay 15
Delay 3
Delay 1 S5 S4
110 101
Output 100100 Output 010100

begin S1: if(count < SEC1)
if (clr == 1) begin
module traffic ( begin state <= S1;
input wire clk , state <= S0; count <= count + 1;
count <= 0; end
input wire clr , end else
output reg [5:0] lights else begin
); case(state) state <= S2;
S0: if(count < count <= 0;
reg[2:0] state; SEC5) end
reg[3:0] count; begin S2: if(count < SEC1)
parameter S0 = 3'b000, S1 =3'b001, S2 = 3'b010, // state <= S0; begin
states count <= count + state <= S2;
1; count <= count + 1;
S3 = 3'b011, S4 = 3'b100, S5 = 3'b101;
end end
parameter SEC5 = 4'b1111, SEC1 = 4'b0011; // else else
delays begin begin
always @(posedge clk or posedge clr) state <= S1; state <= S3;
count <= 0; count <= 0;
end end
S3: if(count < SEC5) S4: if(count < SEC1) S5: if(count < SEC1)
begin
begin begin state <= S5;
state <= S3; state <= S4; count <= count + 1;
count <= count + 1; count <= count + 1; end
end
end else
else begin
else state <= S0;
begin count <= 0;
begin
state <= S5; end
state <= S4; count <= 0; default state <= S0;
count <= 0; end endcase
end end
always @(*)
begin
case(state)
S0: lights = 6'b100001;
S1: lights = 6'b100010;
S2: lights = 6'b100100;
S3: lights = 6'b001100;
S4: lights = 6'b010100;
S5: lights = 6'b100100;
default lights = 6'b100001;
endcase
end
endmodule
Test Bench for Traffic light controller
initial begin
// Initialize Inputs
clk = 0;
clr = 0;
#2;
clr = 1;
#2;
clr = 0;
#2;
// Add stimulus here
end
always #5 clk = ~clk;

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else if (count < 8)

Output 100001 Output 100010 Output 100100 Output 001100;

Output 100100 Output 010100

// Add stimulus here

always #5 clk = ~clk;

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