Digital Systems

(18B11EC213)
Lect-03
 Data Representation

In the conventional arithmetic system, a negative number is

represented by a minus sign and a positive number by a plus sign.

 But in digital systems, computers take input data in the form of

binary, also referred to as ‘bits.’

January 1, 2023
 Note: In all four representation, positive number is represented in the
same way. Thus, we have focus on only negative binary number.

January 1, 2023
Signed Magnitude Representation

• Signed Magnitude (SM) is a method for encoding signed

integers.
• The Most Significant Bit (MSB) is used to represent the sign.
• ‘1’ is used for a ‘-’ (negative sign),
• ‘0’ for a ‘+’ (positive sign).
Format of SM Representation:
• The format of a SM number in 8 bits is:
smmmmmmm
• Where ‘s’ (MSB) is the sign bit
• The other 7 bits represent the magnitude.
• NOTE: for positive numbers, the result is the same as the
unsigned binary representation.
January 1, 2023
 Unsigned Magnitude: We can represent only positive binary number.
Ex. +6 = 110
-6 = we can not represent.
Note: Range varies from 0 to 2n – 1. where, n is number of variable.
Signed Magnitude: We can represent both positive and negative binary number.
Ex. +6 = 0110 Note: 0 + Ve number and 1 - Ve
number
-6 = 1110 Magnitude They are sign bit or MSB

Ex. + 15 = 01111
- 15 = 11111
For n-bits, its range varies from – (2n-1 – 1) to + (2n-1 – 1).
Ex. n = 4, its range varies from -7 to 7

January 1, 2023
1’s Complement

1’s Complement: We can represent both positive and negative binary number.
• In the binary, if we replace each ‘0’ by ‘1’ and it’s vice-versa, the final result is the 1’s complement
of the original binary number.

• In this type, positive numbers are represented with normal binary and their MSB as ‘0’ and
negative numbers with MSB as ‘1.’

• To find the 1’s complement of a negative number, we have to follow a few steps:-
• Step 1:- Write binary of positive number.
• Step 2:- Its 1’s complement
• Example:
Q.1 Find 1’s complement of  -13.  
Step 1:- +13 =  01101
Step 2:-  -13 =  10010 (1’s complement)  
Q.2 Find 1’s complement of  -6.  
Step 1:- +6 =  00110
Step 2:-  -6 =  11001 (1’s complement)  

January 1, 2023
2’s Complement

2’s Complement : We can represent both positive and negative binary number.
• By adding ‘1’ to the one’s complement representation of a binary number, we will
obtain the final result as 2’s complement of the original number.
• In this type, positive numbers are represented with normal binary and their MSB
as ‘0’ and negative numbers with MSB as ‘1.’ To find the 2’s complement, but to
represent a negative number, we have to follow a few steps:-
• Step 1:- Write binary of positive number.
• Step 2:- It’s 1’s complement.
• Step 3:- add ‘1’ in the result of step 2 using binary addition.

January 1, 2023
Example

What is -5 in Two’s Complement, 8 bits?

The magnitude 5 in 8-bits is:
(00000101)2 = (05)16

Now complement each bit:

(11111010)2 = (FA)16

Now add one: (FA) 16 + 1 = (FB)16

(FB)16 is the 8-bit, two’s complement representation of -5.

For n-bits, its range varies from – (2n-1 ) to + (2n-1 – 1).
Ex. n = 4, its range varies from -8 to 7

January 1, 2023
Complement in Different Number System

Here ‘R’ is depicting radix or base. The R’s complement is further sub-classified
into two types:-
(i) (R-1)’s complement (ii) R’s complement

January 1, 2023
 (R-1)’s and R’s complement representation
We need to follow a few steps to find the (R-1)’s complement of any number.

Step 1: – For the given base number system, write the maximum possible number.

Step 2:- Subtract the given number from the maximum possible number. This is (R-1)`s
complement
Step3:- R`s complement = (R-1)`s complement +1
Example 1
Find the 1’s complement of a binary number 1001. And also find the 2’s complement.
Solution:-
For 1’s complement
Step 1:- In a binary number system, maximum possible 4 digit binary number is 1111.
Step 2:- Subtract 1001 from 1111.
We obtain 1’s complement as = 1111  –  1001  
  
                                                    = 0110
For 2’s complement

For 2’s complement = 1’s complement +1

0110+1 = 0111

January 1, 2023
 Example 2
Find the 7’s complement of an octal number 5667. And also find the 8’s complement.

Solution:-
For 7’s complement

Step 1:- In an octal number system maximum possible 4 digit number is 7777.
Step 2:- Subtract 5667 from 7777.
We obtain 7’s complement as = 7777  –  5667  
                                                      = 2110

For 8’s complement

For 8’s complement = 7’s complement +1

2110+1 = 2111

January 1, 2023
 Example 3
Find the 9’s and 10’s complement of a decimal number 2669.
Solution:-
For 9’s complement
Step 1:- In a decimal number system maximum possible 4 digit number is 9999.
Step 2:- Subtract 2669 from 9999.
We obtain 9’s complement as = 9999  –  2669  
                                                      = 7330
For 10’s complement

For 10’s complement = 9’s complement +1

7330+1 = 7331

Example 4
Find the F’s complement of Hexadecimal number 2688.
Solution:-
For F’s complement
Step 1:- In a hexadecimal number system maximum possible 4 digit number is FFFF.
Step 2:- Subtract 2688 from FFFF.
We obtain F’s complement as = FFFF  – 2668  
                                                      = D977

January 1, 2023
 Binary subtraction using 1`s complement

Step:-01 convert number to be subtracted to it`s 1`s compliment form.

Step:-02 Perform the addition.
Step:-03 (i) If the final carry is 1, the add it to the result obtained in step no. 2.
(ii) If final carry is 0, result obtained in step no. 2 is negative and in the 1`s
complement form.

Ex. Perform (1100)2 - (0101)2

A =1100 A + (-B)
B =0101

(-B) = Take 1`s complement of B = 1010

Add A+(-B) = 1100+1010 = 10110 since carry is one
0110+1 = 0111
Ex. Perform (0101)2 - (1100)2
A=0101 A + (-B)
B=1100
(-B) = Take 1`s complement of B = 0011
Add A+(-B) = 0101+0011 = 1000, since there is no any carry.
Therefore, take complement of 1000 for final result = -(0111) = -(7)

January 1, 2023
 Binary subtraction using 2`s complement

Step:-01 convert number to be subtracted to it`s 2`s compliment form.

Step:-02 Perform the addition.
Step:-03 (i) If the final carry is 1, the no add it to the result obtained in step no. 2.
(ii) If final carry is 0, result obtained in step no. 2 is negative and in the 2`s
complement form.

Ex. Perform (1001)2 - (0100)

A =1001 A + (-B)
B =0100

(-B) = Take 1`s complement of B+1 = 1011+1= 1100

Add A+(-B) = 1001+1100 = 10101 since carry is one, so neglect it.
= 0101
Ex. Perform (0110)2 - (1011)2
A=0110 A + (-B)
B=1011
(-B) = Take 1`s complement of B+1 = 0100+1 = 0101
Add A+(-B) = 0110+0101 = 1011 since carry is zero
Therefore, take 2`s complement of 1011 to get final result = -(0100+1)= -(0101 = -(5)

January 1, 2023
Digital SystemsS
(18B11EC213)
Lect-04
 Binary subtraction using 9`s complement

Q. Find X-Y using 9`s complement.

where, X = 7235 and Y= 5327

Sol: We can write X – Y in this X+(-Y)

For (-Y) = 9`s complement of Y = 9999

-5327
4672

Add X+(-Y) = 7235+4672 = 11907, since carry is one, so neglect it.

For final result = add carry with 01907

01907
+ 1
01908

January 1, 2023
 Binary subtraction using 9`s complement

Q. Find Y-X using 9`s complement.

where, X = 7235 and Y= 5327

Sol: We can write Y – X in this Y+(-X)

For (-X) = 9`s complement of X = 9999

-7235
2764

Add Y+(-X) = 5327+2764 = 8091,

since there is no any carry.
Take complement of 8091 to final result = 9999-8091 = -(1908) Ans

January 1, 2023
 Binary coded decimal code (BCD)
Each digit of decimal number is represented by binary equivalent.

In4-binary formats
Total number of possible representation = 24 = 16
Valid BCD codes = 10
Invalid BCD code = 16-10 = 6
Positional weights are 8-4-2-1, it is also call BCD code.

In 8-binary formats
Total number of possible representation = 28= 256
Valid BCD codes = 100
Invalid BCD code = 256-100 = 156

January 1, 2023
 Binary coded decimal code (BCD)
Decimal Binary Coded
number Decimal(BCD)
0 0000
1 0001
2 0010 Decimal
(15)10
3 0011
number
4 0100
5 0101 Valid BCD
6 0110
7 0111 Decimal digit
8 1000
9 1001

10 Xxxx
Conversion of Decimal to BCD
11 Xxxx
Ex.
12 Xxxx
Invalid BCD (9)10 = 1001
13 Xxxx
14 Xxxx
(10) 10 = 0001 0000
15 Xxxx (19)10 = 0001 1001

January 1, 2023
 Comparison of Binary and BCD numbers

(10)10= (1010)2 (0001 0000)BCD

(13)10 = (1011)2 (0001 0011)BCD

Excess -3 code

Add(3)
Decimal 8-4-2-1 (BCD) Excess- 3
It is a 4 bit code.
It can be derived from BCD code by adding 3 of each code number.

Ex . 8 8+3 = 11

(1000)2 (1000)BCD+ 0011 = 1011

January 1, 2023
 Decimal number Binary Coded Decimal(BCD) Excess-3

0 0000 0011
1 0001 0100
2 0010 0101
3 0011 0110
4 0100 0111
5 0101 1000
6 0110 1001
7 0111 1010
8 1000 1011
9 1001 1100

Excess-3 code= Un-weighted code which is self complement code

January 1, 2023
 Q. Encode the following decimal numbers in BCD code and Excess-3 code.
a)16
b) 10.23
c)123.56

Sol: we know that BCD code is also called 8421.

BCD code of 16: (00010110)BCD

Excess-3 code = BCD code+3

16 00010110
33 00110011
49 01001001

Therefore, Excess-3 code of 46 = (01001001)Excess-3

January 1, 2023
 Q. Encode the following decimal numbers in BCD code and Excess-3 code.
a)16
b) 10.23
c)123.56

Sol: we know that BCD code is also called 8421.

BCD code of 10.23: (00010000.00100011)BCD

Excess-3 code = BCD code+3

10.23 00100000.00100011
.33.33 00110011 .00110011
43.56 01000011.01010110

Therefore, Excess-3 code of 46 = (01000011.01010110)Excess-3

January 1, 2023
 Q. Encode the following decimal numbers in BCD code and Excess-3 code.
a)16
b) 10.23
c)123.56

Sol: we know that BCD code is also called 8421.

BCD code of 123.56: (000100100011.01010110)BCD

Excess-3 code = BCD code+3

123.56 000100000010.01010110
.333.33 00110011 0011.00110011
456.89 010001010110.10001001

Therefore, Excess-3 code of 46 = (01000101011010001001)Excess-3

January 1, 2023
 Gray Code
Gray code is useful because only one bit changes
at a time, which is implemented easily in Coded
representation of a shaft’s mechanical position. In
Gray Code, every sequence of successive bits
differs by 1 bit only.

Procedure: Binary to Gray code Ex.1 (11101)2 = (?)Gray

(11101)2 = (10011)Gray

Ex.2 (010101)2 = (?)Gray

(010101)2 = (011111)Gray

Ex.3 (1100)2 = (?)Gray

(1100)2 = (1010)Gray

January 1, 2023
 Gray code conversion

They are two types of conversion

a)Binary to gray conversion
b)Gray to binary conversion

Procedure: Gray to Binary Code Ex.1 (10011)Gray = (?)2

(10011)Gray = (11101)2

Ex.2 (010101)Gray = (?)2

(010101)Gray = (011001)2

Ex.3 (1101)Gray = (?)2

(1101)Gray = (1001)2

January 1, 2023
 Boolean Algebra

George Boole (1815-1864) applied a set of symbols to logical operations.

Digital electronics applies his set theory and logic to (binary) switching
networks.

Binary number system is used to represent the two possible states of our
systems.
 The symbols 0 & 1 are used to represent:
True or False
Flow or No Flow
Open or Closed
Voltage1 or Voltage2
etc.

•Deals with manipulation of Variables & Constants

•Boolean Variables, such as X, Y, Z, A, B, C, etc. can have "values“ of
either 0 or 1. .

• 0 & 1 are constants & are symbols only, representing two different states
of a quantity.
January 1, 2023
 Boolean Algebra

F or T
Low voltage or high voltage, usually written L or H
Flow or not flow
e.g. 0V  logical 0 + ve
logic
+5V  logical 1
or 0V  1 - ve
logic
+5V  0

The Boolean 0 and 1 represents the logic level.

Logic 0 Logic 1
False True
OFF ON
Low High
No Yes
January 1, 2023Open switch Close Switch
Digital Systems
(18B11EC213)
Lect-05
 Truth table and Logic Gates

Truth Table: A Truth table is a means of describing how a logic circuits output depends
on the logic levels present at circuits input.
The number of input combinations will equals to 2N for the N input in the truth table.

The logics gate can be classified:

a)Basic Gate: NOT, AND, OR.

b)Universal Gate: NAND, NOR.
c)Special Purpose Gates: EX-OR and EX-NOR.
They are used in arithmetic's circuits, Code conversion, and comparators etc.

January 1, 2023
January 1, 2023
 Introduction of Boolean Algebra

Set of Rules such OR/AND/NOT/ Demorgan`s, Involution law etc.

It is a set of rules used to simplify the logic expression without changing its
functionality.

It is used when number of variables are less(1,2,3)

It is preferred when output is 0 or 1.

K-Map:
 When number of variables are 2,3,4,5 ( upto 5 variable)

Output is 0,1 or x.

Tabular Method:

It is used when number of variables are more.

January 1, 2023
Set of Rules:

 A complement A ` or A
NOT: 0 = 1
1=0
AND: OR
Truth Table Truth Table
X Y F X Y F
X Y F X Y F
0 0 0 A A A
0 0 0 A A A
0 1 1 A 1 1
0 1 0 A 1 A
1 0 1 A 0 A
1 0 0 A 0 0
1 1 1 A A` 1
1 1 1 A A` 0

For Example: For Example:

January 1, 2023
January 1, 2023
 Introduction of Boolean Algebra
.
 For Example
F = ABC+ BC (Given function) ( 2 AND gate + 1 gate OR = 3 gate)

F = BC (Simplified form) ( It requires only 1 AND gate)

A
B AND
C OR ABC+ BC

B AND
C

Merits of Simplification of function:

Less cost due to less number of gate

Space very less due to reduction of numbers of gate
Power dissipation decrease due to reduction of numbers of gate

January 1, 2023
 Reduction Techniques of Boolean Algebra
There are the following rules of Boolean algebra, which are mostly used in manipulating
and simplifying Boolean expressions. These rules plays an important role in simplifying
Boolean expressions.:

January 1, 2023
 Examples

Q.1 F(A, B, C) = F = AB+AB` Simplify the Boolean function.

= A.(B+B`) [Complement law B+B` = 1]
= A.1 = A [Identify AND law A.1 =A]

`Q.2 F = (A+B).(A+C), Simplify the Boolean function.

= A.A+A.C+B.A+B.C [Distributive law]

= A+A.C+A.B+B.C [Idempotent AND law A.A =A]

= A (1+C)+ A.B+B.C [Distributive law]

= A.1+A.B+B.C [Identify OR law (1+C =1)]

= A(1+B)+B.C [Distributive law]

= A.1+B.C [Identify OR law (1+B =1)]

= A+BC
January 1, 2023
 Ex.3 F(A, B, C) = (A+B)B' + B' + BC, Simplify the Boolean function.

Sol: We use the Distributive Law [(A+B)B' = AB' + BB']:

F(A, B, C) = AB' + BB' + B' + BC

We use one of the Complement Law(BB' = 0) and afterwards

the Identity of Addition (AB' + 0 = AB'):

F(A, B, C) = AB' + B' + BC

We take a common factor B' of the first two:

F(A, B, C) = B'(A + 1) + BC

We use the Annihilator of Addition (A + 1 = 1) and afterwards the Identity of

Multiplication (B '* 1 = B'):
F(A, B, C) = B' + BC
We use the Complement Law (B' + BC = B' + C):
F(A, B, C) = B' + C
January 1, 2023
 Ex.4 F(A, B, C) = ABC+BC, Simplify the Boolean function.

= (A+1)BC
= BC

Ex.5 F(A, B, C) = AAB+ABB+BAB`, Simplify the Boolean function

= AB+AB+ABB`
= AB+AB+ABB`
= AB+ABB`
= AB(1+B`)

Ex.6 F(A, B, C) = (A+B+C) +(B+C), Simplify the Boolean function

= (A+B+C)(B+C)

=(A B C) (B C) = 0

January 1, 2023
 Ex.7 F(A, B, C) =(A+B+C) (A+B) , Simplify the Boolean function.

= (AA+AB+BA+BB+CA+CB

= (A+AB+B+CA+CB)

= (A(1+B)+B+CA+CB)

= (A+B+CA+CB)

= ((A+B)+C(A+B))

= ((A+B)(1+C))

= (A+B)

January 1, 2023
Digital Systems
(18B11EC213)
Lect-06
 Boolean Function Representation (SOP and POS)

Canonical form: All the terms contains each literal.

Ex. F(A, B, C) = A`BC+ ABC+ A`BC`

Standard form: All the terms do not contain each literal.

Ex. F(A, B, C) = A`+ BC+ A`BC`

Note: A binary variable is called Literal.

Min-terms : It is in product form. It is denoted by m.

Ex. ABC or BC or ABCDE

max-terms:- It is in sum form. It is denoted by M.

Ex. A+B+C or B+C or A+B+C+D+E

n-binary variable have 2n possible combinations each of theses possible

combination is called min-terms or standard product form (SOP).
January 1, 2023
 SOP ( Sum of Product):
Total number of combination = 2n , where n is variable.
SOP form is used when output logic is “1”.

It can represent in SOP form.

D Index X Y F
It can represent in POS form.
0 m0 0 0 0
1 m1 0 1 1 Note: 1 X and 0 X`

2 m2 1 0 0 Ex. (3) = 11 = X.Y

3 m3 1 1 1 (1) = 01 = X`.Y

F (X,Y) = F = X`Y+XY

Product term F can be written as F(X,Y) = m1+m3 = ∑ m(1, 3) =Y

Min-terms or impilicants.
January 1, 2023
 SOP ( Sum of Product):
Total number of combination = 2n , where n is variable.
SOP form is used when output logic is “1”.
Note: 1 X and 0 X`

D Index X Y Z F
0 m0 0 0 0 0
1 m1 0 0 1 1 F (X,Y) = F = X`Y`Z+X`YZ+XY`Z`
2 m2 0 1 0 0

3 mF3 (X,Y)0 = F1= X`Y+XY
1 1
4 
m4 1 0 0 1 F(X,Y,Z) = m1+m3+m4 = ∑ m(1,3, 4)
5 m5 1 0 1 0
6 m6 1 1 0 0
7 . m7 1 1 1 0

January 1, 2023
 Q. For given truth table, minimize SOP expression.

A B F
0 0 1
0 1 0
1 0 1
1 1 0

Sol: In SOP form, only “1” is taken. D A B F

0 A`B` 0 0 1
= A`B`+AB` 1 A`B 0 1 0
= B`(A`+A)
= B` 2 AB` 1 0 1
3 AB 1 1 0

F can be written as F(A,B) =∑ m(0, 2) = B`

January 1, 2023
 POS( Product of Sum):
Total number of combination = 2n , where n is variable.
POS form is used when output logic is “0”.

It can represent in SOP form.

D Index X Y F
It can represent in POS form.
0 M0 0 0 0
1 M1 0 1 1 Note: 0 X and 1 X`

2 M2 1 0 0 Ex. (0) = 0 0 = X+Y

3 M3 1 1 1 (2) = 1 0 = X`+.Y

F (X,Y) = F = (X+Y)(X`+Y)

Sum term F(X,Y) = M0.M2 = ∏ m(0, 2)

Max-terms or impilicants.
January 1, 2023
 POS( Product of Sum):
Total number of combination = 2n , where n is variable.
POS form is used when output logic is “0”.
Note: 1 X` and 0 X

D Inde X Y Z F
x
0 M0 0 0 0 0 F (X,Y) = F = (X+Y+Z) (X+Y`+Z) (X`+Y+Z`) (X`+Y`+Z)
1 M1 0 0 1 1
2 
MF2 (X,Y)
0 = 1F = X`Y+XY
0 0

3 M3 0 1 1 1
F(X,Y) = M0.M2..M5.M6 = ∏ m(0, 2, 5, 6 )
4 M4 1 0 0 1
5 .M5 1 0 1 0
6 M6 1 1 0 0
7 M7 1 1 1 1

January 1, 2023
 Q. For given truth table, minimize POS expression.

A B F
0 0 1
0 1 0
1 0 1
1 1 0

Sol: In POS form, only “0” is taken. D A B F

0 A+B 0 0 1
= (A+B`)(A`+B`) 1 A+B` 0 1 0
= AA`+AB`+B`A`+B`B`
= 0+ AB`+AB`+B` 2 A`+B 1 0 1
= AB`+B`= B`(A+1) = B` 3 A`+B` 1 1 0

F can be written as F(A,B) = ∏M(1 ,3) = B`

F can be also written as F(A,B) =∑ m(0, 2) = B` [ Note: SOP = POS]
January 1, 2023
 Q. If F(A, B) = ∑ m(0, 1,). Find POS form or max- terms.

Sol: Since, there are 2 variables , hence 4 combination is possible.

i.e. {0,1,2,3}

For max term = 2, 3

F(A,B) = ∏M(2, 3) = 10 11 = (a`+b)(a`+b`)

F = ∑ m(0, 1). = ∏M(2, 3) [ Note: SOP = POS]

January 1, 2023
 Q. If F(A, B, C) = ∑ m(0, 1, 4, 7). Find POS form or max-terms.

Sol: Since, there are 3 variables, hence 8 combination is possible.

i.e. {0,1,2,3,4,5,6,7}

For max term = 2, 3, 5, 6

F(A,B, C) = ∏M(2, 3, 5, 6) = (010, 011, 101, 110)

= (A+B`+C)(A+B`+C`)(A`+B+C`)(A`+B`+C)

F = ∑ m(0, 1, 4, 7). = ∏M(2, 3, 5, 6) [ Note: SOP = POS]

https://www.gatevidyalay.com/k-maps-karnaugh-maps-solved-examples/

January 1, 2023
 Gray Code
Gray code is useful because only one bit changes
at a time, which is implemented easily in Coded
representation of a shaft’s mechanical position. In
Gray Code, every sequence of successive bits
differs by 1 bit only.

Procedure: Binary to Gray code Ex.1 (11101)2 = (?)Gray

(11101)2 = (10011)Gray

Ex.2 (010101)2 = (?)Gray

(010101)2 = (011111)Gray

Ex.3 (1100)2 = (?)Gray

(1100)2 = (1010)Gray

January 1, 2023
Digital Systems
(18B11EC213)
Lect-07
Contents

This lecture will cover: –

 Karnaugh Maps (K-Map)

Types of variable (2, 3, 4)

Rules of Simplification of Boolean Function

January 1, 2023
 Introduction of Boolean Algebra

Set of Rules such OR/AND/NOT/ Demorgan`s, Involution law etc.

It is a set of rules used to simplify the logic expression without changing its
functionality.

It is used when number of variables are less(1,2,3)

It is preferred when output is 0 or 1.

K-Map:
 When number of variables are 2,3,4,5 ( upto 5 variable)

Output is 0,1 or x.

Tabular Method:

It is used when number of variables are more.

January 1, 2023
 Introduction of Boolean Algebra

Karnaugh Map-

For a Boolean expression consisting of n-variables, number of cells required in

K Map = 2n cells.
It follows adjunct rule i.e. only 1 variable change and 2 variable change does
not allow.
It follows A+A` = 1
Types of representation:
A)SOP form representation Ex. F(A,B) =∑ m(0, 2) = m0+m2 = A`B`+ AB` =
B)POS form representation Ex. F(A,B) = ∏M(1 ,3) = M0.M3 = (A+B`) (A`+B`)
January 1, 2023
 Two Variable K Map-
 
Two variable K Map is drawn for a Boolean expression consisting of two
variables.
The number of cells present in two variable K Map = 22 = 4 cells.
So, for a Boolean function consisting of two variables, we draw a 2 x 2 K Map.
 
Two variable K Map may be represented as-

January 1, 2023
 Three Variable K Map-
 
Three variable K Map is drawn for a boolean expression consisting of three
variables.
The number of cells present in three variable K Map = 23 = 8 cells.
So, for a Boolean function consisting of three variables, we draw a 2 x 4 K
Map
Three variable K Map may be represented as-

January 1, 2023
 Four Variable K Map-
 
Four variable K Map is drawn for a boolean expression consisting of four variables.
The number of cells present in four variable K Map = 24 = 16 cells.
So, for a boolean function consisting of four variables, we draw a 4 x 4 K Map.
 
Four variable K Map may be represented as-

January 1, 2023
Digital Systems
(18B11EC213)
Lect-08
 Karnaugh Map-

For a Boolean expression consisting of n-variables, number of cells required in

K Map = 2n cells.
It follows adjunct rule i.e. only 1 variable change and does not allow 2 variable
change.
It follows A+A` = 1
K-Map also represent in two form:
A)SOP form representation Ex. F(A,B) =∑ m(1, 3) = m1+m3 = A`B+ AB = B
B)POS form representation Ex. F(A,B) = ∏M(0,2) = M0.M2 = (A+B) (A`+B) = B

Number Variable Output Sum of product (SOP) Product of Sum (POS)

D A B F Index Min Index Max

Terms Terms
0 0 0 0 m0 M0 A+B
1 0 1 1 m1 A`.B M1
2 1 0 0 m2 M2 A`+B
3 1 1 1 m3 A.B M3
January 1, 2023
 Karnaugh Map Simplification Rules in SOP-

 No zeros is allowed.

0 0 1 0
1 0 1 0

 No diagonal is allowed.
0 1 0 0
1 0 1 1

 Only power of 2 number of cells in each group. 1 0 0 1

0 0 1 0 1 1 1 1 1 1 1 1 1 0 0 1
1 0 1 0 0 0 0 0 1 1 1 1 1 0 0 1
1 0 0 1
 Three and five grouping are not allowed.

1 1 1 0
0 0 0 0
January 1, 2023
 Karnaugh Map Simplification Rules in SOP-

 Every one must be in at least one group.

1 0 0 0 0 0 0 1
0 1 1 0 1 0 1 0
 Overlapping allowed.

1 1 0 1 1 1 1 1
1 0 1 1 0 1 0 1

 Wrap around allowed. 1 0 0 1

1 0 0 1 0 1 1 0
1 0 0 1 1 0 0 1 1 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0
1 0 0 1 1 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0
1 0 0 1 0 1 1 0 1 0 0 1
 Fewest number of group possible.

0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 1 0 0 0 0 0 1 1 0 1 1 1 1
January 1, 2023
 For Two Variable: Given the function F(A, B) = A`B+AB in SOP form. Simplify it.

B 0 1
D Inde Min A B F A A`B ` A`B
x Terms 0
0 m0 A`.B` 0 0 0 m0 AB` AB
1
1 m1 A`.B 0 1 1 m1
B 0 1
2 m2 A.B` 1 0 0 m2 A
00 01
0
3 m3 A.B 1 1 1 m3
10 11
1
Note: A = MSB

B 0 1
B` B A` A A
B A 0 1 0 1
0 1 B 0
A m0 m2
A` 0 m0 m1
B` 0 (00) (10) 1 0 1
(00) (01)
A 1 m2 m3 or B 1 m1 m3
F = A`B+AB = B(A+A`) = B
(10) (11) (01) (11) F(A,B) =∑ m(1, 3)
January 1, 2023
 Examples of SOP form for two variable

Pairing of 1`s = 2n
B` B
B 1 1`s
0 1 2 1`s
A
A` 0 0 1 F = A`B+AB = B(A+A`) = B 4 1`s
8 1`s
A 1 0 1 B 16 1`s so on
0 1
A Take prime group first
0 1 1 F = A`+B
B 1
0
A 0 1
0 1 1 A
B
0 1
F = A`
1 0 0 B
0 0 1 F = A+B
A 0 1
0 1 1 1 1 1
F = A`+B`
B
A 0 1 1 0
0 1 0 B
F = B` 0 1
A
1 1 0 0 1 1 F=1
B 0 1
A 1 1 1
B
0 1
0 1 0 F = A+B` B
A 0 1
0 0 0 1 1 1 A
0 0 1 F = A`B+AB`
F=A
1 1 1 1 1 0
January 1, 2023
Given the function F(A, B) = (A+B)(A`+B`) in POS form. Simplify it.

B 0 1
D Inde Max A B F A A+B A+B`
x Terms 0
0 M0 A+B 0 0 0 m0 A`+B A`+B`
1
1 M1 A+B` 0 1 1 m1
B 0 1
2 M2 A`+B 1 0 0 m2 A
00 01
0
3 M3 A`+B` 1 1 1 m3
10 11
1
Note: A = MSB

B 0 1
B B` A A` A
B A 0 1 0 1
0 1 B 0
A M0 M2
A 0 M0 M1
B 0 (00) (10) 1 0 1
(00) (01)
A` 1 M2 M3 or B` 1 M1 M3 F = (A+B) (A`+B`) = B
(10) (11) (01) (11) F(A,B) = ∏M(0,2)
January 1, 2023
For Three Variable:
Given the function F(A, B, C) = AB`C`+A`C in SOP form. Simplify it.

D Inde A B C F Min term Note: 1 A and 0 A`

x BC
m0 A 00 01 10 11
0 m0 0 0 0 0 A`B`C`
A`=0 m0 m1 m2 m3
m1
1 m1 0 0 1 1 A`B`C
A=1 m4 m5 m6 m7
m2
2 m2 0 1 0 0 A`BC`
m3
3 m3 0 1 1 1 A`BC
m4 BC 00 01 10 11
4 m4 1 0 0 1 AB`C` A
m5 000 001 010 011
5 m5 1 0 1 0 AB`C A` =0 (0) (1) (2) (3)
m6
6 m6 1 1 0 0 ABC` 100 101 011 111
A= 1 (4) (5) (6) (7)
7 m7 1 1 1 0 ABC m7

BC
A 00 01 11 10
It follows adjunct rule i.e. only 1
000 001 011 010
variable change and does not allow 2 A`= 0 (0) (1) (3) (2)
variable change.
It follows A+A` = 1 100 101 111 110
A= 1
(4) (5) (7) (6)
January 1, 2023
 BC 11 10
Unit distance change = 00-01-11-10 ` A 00 01
A+A` = 1 0 m0 m1 m3 m2

C 1 m4 m5 m7 m6
.

BC 00 01 11
A 10
0 0 1 1 0
F (A,B,C) = A`C+AB`C`
1 1 0 0 0
F(A,B) =∑ m(1, 3, 4)
AB`C

Pairing of 1`s Note: Rule of one variable change

1 1`s 0 0 0 0
2 1`s
4 1`s 0 1 0 1
81`s 1 0 1 1
161`s so on
1 1 0 1
Always start from prime group
January 1, 2023
Digital Systems
(18B11EC213)
Lect-09
 Examples of SOP form for Three variable
F(A, B, C) = ∑ m(1, 2, 4, 7) F(A, B, C) = ∑ m(1, 2, 3, 4, 6, 7)
F(A, B, C) = ∑ m(0, 2, 4, 6)
BC 00 01
BC
00
`
01 11 10 BC
11 10 A 00 01 11 10
A A
0 0 1 1 1
0 0 1 0 1 0 1 0 0 1
1 0 0 1 1 1
1 1 0 1 0 1 0 0 1
F(A, B, C) = A`B`C+A`B C`+AB`C`+ABC F(A, B, C) = A`C+B F(A, B, C) = C`

F(A, B, C) = ∑ m(1, 3, 4) F(A, B, C) = ∑ m(0, 1, 2, 3, 4, 5, 7) F(A, B, C) = ∑ m(0, 1, 2, 4 )

BC BC BC
00 01 11 10 A 00 01 11 10 A 00 01 11 10
A
0 0 1 1 0 0 1 1 1 0 0 1 1 0 1
1 1 0 0 0 1 1 1 1 0 1 1 0 0 0
F(A, B, C) = A`C+AB`C`
F(A, B, C) = B`+C F(A, B, C) = B`C`+A`
F(A, B, C) = ∑ m(1, 3, 5, 7) F(A, B, C) = ∑ m(0, 1, 2, 3, 4, 5, 6, 7)
BC F(A, B, C) = ∑ m(0, 1, 2, 3, 5, 7)
A 00 01 11 10
BC
0 0 1 1 1 00 01 11 10
A 00 01 11 10
0 1 1 1 1 1 1 1 1
1 1 1 1 0 0
1 1 1 1 1 1 0 1 1 0
F(A, B, C) = AB`C`+ C+AB`+A`B`

F(A, B, C) = 1 F(A, B, C) = A`+C

January 1, 2023
For Three Variable:
Given the function F(A, B, C) = (A+B+C)(A+B`+C)(A`+B+C`)(A`+B`+C)(A+B+C) in POS
form. Simplify it.
Note: 0 A and 1 A`
D Inde A B C F Max
x terms BC A+B A+B`+ A`+B A`+B`
M0 A 00 01 10 11
0 M0 0 0 0 0 A+B+C
A=0 M0 M1 M2 M3
M1
1 M1 0 0 1 1 A+B+C`
A`=1 M4 M5 M6 M7
M2
2 M2 0 1 0 0 A+B`+C
3 M3 0 1 1 1 A+B`+C`
M3 A+B A+B`+ A`+B A`+B`
BC
M4 00 01 10 11
4 M4 1 0 0 1 A`+B+C A
M5 000 001 010 011
5 M5 1 0 1 0 A`+B+C` A =0 (0) (1) (2) (3)
M6
6 M6 1 1 0 0 A`+B`+C 100 101 011 111
A`= 1 (4) (5) (6) (7)
7 M7 1 1 1 0 A+B+C M7

BC A+B A+B`+ A`+B` A`+B

A 00 01 11 10
It follows adjunct rule i.e. only 1
000 001 011 010
variable change and does not allow 2 A= 0 (0) (1) (3) (2)
variable change.
It follows A+A` = 1 100 101 111 110
A`= 1
(4) (5) (7) (6)
January 1, 2023
 BC B+C B+C`+ B`+C` B`+C
A `
00 01 11 10 Pairing of 1`s
.
A 0 1 0`s
0 0
2 0`s
A`1 0 0 0
4 0`s
80`s
160`s so on
F (A,B,C) = (A+C)(B`+C)(A`+C`) Always start from prime group

F(A,B) = ∏M(0, 2, 5, 6, 7)

Note: Rule of one variable change

0 0 0 0
0 1 0 1
1 0 1 1
1 1 0 1
January 1, 2023
 SOP POS
F(A, B, C) = ∏M (0, 3, 5, 6)
F(A, B, C) = ∑ m(1, 2, 4, 7)
BC BC B+C B+C` B`+C` B`+C
B` C ` B` C BC B C`
A 00 01
` 11 10
A 00 01 11 10
A` 0 1 1 A 0 0 0
A 1 1 1 A` 1 0 0
F(A, B, C) = (A+B+C)(A+B`+C`)(A`+B+C`)(A`+B`+C)
F(A, B, C) = A`B`C+A`B C`+AB`C`+ABC

F(A, B, C) = ∑ m(1, 3, 4) F(A, B, C) = ∏M (0, 2, 5, 6, 7)

B` C ` B` C BC B C` BC B+C B+C` B`+C` B`+C
BC
00 01 11 10 A 00 01 11 10
A
0 1 1 A 0 0 0 F(A, B, C) = (a+C)(B`+C)(A+C)
1 1 A` 1 0 0 0
F(A, B, C) = A`C+AB`C`

F(A, B, C) = ∑ m(1, 3, 5, 7) F(A, B, C) = ∏M (0, 2, 4, 6 )

BC B` C ` B` C BC B C`
A 0 0 0 1 1 1 10 BC B+C B+C` B`+C` B`+C
0 1 1 A 00 01 11 10
A 0 0 0
1 1 1 F(A, B, C) = c
A` 1 0 0
F(A, B, C) = c

January 1, 2023
Digital Systems
(18B11EC213)
Lect-10
4-Variable Representation K-Map in SOP form:
F(A, B, C, D) = ∑ m(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)

CD C`D` C`D CD CD`

AB
00 01 11 10
00 00 00 01 00 11 00 10
A`B` 00 A`B`C`D` A`B`C`D A`B`CD A`B`CD
m0 m1 m3 m2 no. of cell = 2n, where n is the no.
of variable.
01 00 01 01 01 11 01 10 Ex. no. of cell = 24 = 16, range from
A`B 01 A`BC`D` A`BC`D A`BCD` A`BCD (0----15).
m4 m5 m7 m6
11 00 11 01 11 11 11 10
AB 11 ABC`D` ABC`D ABC`D` ABCD
m12 m13 m15 m14
10 00 10 01 10 11 10 10
AB` 10
AB`C`D` AB`C`D AB`CD` AB`CD
m8 m9 m11 m10

January 1, 2023
4- Variable Representation K-Map in POS form:
F(A, B, C, D) = ∏M(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)

C+ D C+ D` C `+ D` C` + D
CD
AB 00 01 11 10
00 00 00 01 00 11 00 10
A+ B 00 A+B+C+D A+B+C+D` A+B+C`+D` A+B+C`+D
M0 M1 M3 M2

01 00 01 01 01 11 01 10
A + B` 01 A+B`+C+D A+B`+C+D` A+B`+C`+D` A+B`+C`+D
M4 M5 M7 M6

11 00 11 01 11 11 11 10
A` + B` 11
A`+B`+C+D A`+B`+C+D` A`+B`+C`+D` A`+B`+C`+D
M12 M13 M15 M14
A` + B 10
10 00 10 01 10 11 10 10
A`+B+C+D A`+B+C+D` A`+B+C`+D` A`+B+C`+D
M8 N9 M11 M10

January 1, 2023
 Examples of SOP
F(A, B, C, D) = ∑ m(1, 2, 4, 7) F(A, B, C, D) = ∑ m(2, 6, 10, 14)
CD C`D` C`D CD CD`
CD C`D` C`D CD CD` AB 00 01 11 10
AB 00 01 11 10
1
1 1 A`B` 00
A`B` 00 m2
m1 m2
A`B 01 1
1 1
A`B 01 m6
m4 m7
AB 11
AB 11 1
AB` 10 m14
AB` 10
1
m10
F(A, B, C, D) = A`BC`D`+ A`B`C`D + A`BCD +A`B`CD`
F(A, B, C, D) = CD`

January 1, 2023
 Examples of SOP
F(A, B, C, D) = ∑ m(2, 3, 6, 7, 8, 9, 12, 13) F(A, B, C, D) = ∑ m(0, 2, 4, 6, 8, 10, 12, 14)

CD C`D` C`D CD CD`

CD C`D` C`D CD CD` AB 00 01 11 10
AB 00 01 11 10
1 1
1 1 A`B` 00
A`B` 00 m0 m2
m3 m2
A`B 01 1 1
1 1
A`B 01 m4 m6
M7 m6
AB 11 1 1
AB 11 1 1
m12 m14
M12 M13
AB` 10
1 1
AB` 10 1 1 m8 m10
M8 M9
F(A, B, C, D) = D`
F(A, B, C, D) = A` C+A C`

January 1, 2023
 Examples of SOP
F(A, B, C, D) = ∑ m(0, 1, 2, 6, 7, 8, 9, 12, 13) F(A, B, C, D) = ∑ m(0, 2, 5, 7, 8, 10, 13, 15)

CD C`D` C`D CD CD`

CD C`D` C`D CD CD` AB 00 01 11 10
AB 00 01 11 10
1 1
1 1 A`B` 00
A`B` 00 m0 m2
m0 m1
A`B 01 1 1
1 1
A`B 01 m5 m7
m7 m6
AB 11 1 1
AB 11 1 1
m13 m15
m12 m13
AB` 10
1 1
AB` 10 1 1 m8 m10
m8 m9
F(A, B, C, D) = B`D`+ B D
F(A, B, C, D) = A C`+B` C`+ A`B C

January 1, 2023
 Variable and Pairing in K-map

F (A, B) = Pairing possible = 4 Produce = 0 variable Ex. F = 1

=2 Produce = 1 variable Ex. F = A
=1 Produce = 2 variable Ex. F = AB

F (A, B, C) = Pairing possible = 8 Produce = 0 variable Ex. F=1

=4 Produce = 1 variable Ex. F=A
=2 Produce = 2 variable Ex. F = AB
=1 Produce = 3 variable Ex. F = ABC

F (A, B, C, D) = Pairing possible = 16 Produce = 0 variable Ex. F = 1

=8 Produce = 1 variable Ex. F = A
=4 Produce = 2 variable Ex. F = AB
=2 Produce = 3 variable Ex. F = ABC
=1 Produce = 4 variable Ex. F = ABCD

January 1, 2023
 5-Variable Representation
Five Variable
K-Map in SOP form:
F(a, b, c, d, D, e) = ∑ m(0, 1, 2, 3, 4, 5, ………………31),

DE D`E` D`E DE DE`

DE D`E` D`E DE DE` BC 00 01 11 10
BC 00 01 11 10
B`C` 00
m16 m17 m19 m18
B`C` 00 m0 m1 m3 m2

m4 m5 m7 m6
B`C 01 m20 m21 m23 m22
B`C 01
BC 11
m12 m13 m15 m14 m28 m29 m31 m30
BC 11

BC` 10
m8 m9 m11 m10 m24 m25 m27 m26
BC` 10

A` = 0 A = 1

no. of cell = 2n, where n is the no. of variable.

Ex. no. of cell = 25 = 32, range from (0----31).

January 1, 2023
 Example-01
F(A, B, C, D, e) = ∑ m(0, 9, 11, 13, 15, 17, 18, 19, 22, 24, 28)

DE D`E` D`E DE DE`

DE D`E` D`E DE DE` BC 00 01 11 10
BC 00 01 11 10
B`C` 00 1 1
B`C` 00 1

B`C 01 1
B`C 01

1 1 BC 11
1
BC 11

1 1 BC` 10 1
BC` 10

A` = 0 A = 1

F(P, A, B, C, D) = a` b`c`d`e`+ A` be + A b`c` e+ a b`c de` + a bd`e`

January 1, 2023
 Example-02
F(a, b, c, d, D, e) = ∑ m(0, 3, 4, 7, 8, 12, 16, 20, 24, 27, 28, 31)

DE D`E` D`E DE DE`

DE D`E` D`E DE DE` BC 00 01 11 10
BC 00 01 11 10
B`C` 00
1
B`C` 00 1 1

1 1
B`C 01 1
B`C 01
BC 11
1 1 1
BC 11

BC` 10
1 1 1
BC` 10

A` = 0 A = 1

F(P, A, B, C, D) = A`D`E`+ A`B`DE+ +AD`E `+ ABDE

= (A`+A) D`E`+ A`B`DE+ABDE

D`E`+ A`B`DE+ABDE

January 1, 2023
 Example-03
F(A, B, C, D, e) = ∑ m(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30)

DE D`E` D`E DE DE`

DE D`E` D`E DE DE` BC 00 01 11 10
BC 00 01 11 10
B`C` 00 1 1
B`C` 00 1 1

1 1 B`C 01 1 1
B`C 01

1 1 BC 11
1 1
BC 11

1 1 BC` 10 1 1
BC` 10

A` = 0 A = 1

F(P, A, B, C, D) = a`E + ae` = e

January 1, 2023
 Implicants: Any group of ‘1’ s can be considered to implicants.
It is a groups of ‘1’. Ex. 1, 2, 4, 8, 16 ……..
Prime Implicants: it is largest possible group of ‘1’.
Octed = 8
Quad = 4
Pair = 2

Essential Prime Implicants: In the group at least, there is single ‘1’ which
can not combine in any other way.
EPI always appear in final solution.

1 1
1 1 I=4 I=8 I=6
PI = 4 1 1 1 PI = 5 1 1 PI = 3
EPI = 4 EPI = 2
1 1 EPI = 4
1 1 1 1 1
1 1

1 1 1 I=5
1 1 1 1 I=6
1 1 I=3
PI = 4 PI = 2
PI = 2 EPI = 2
EPI = 3
EPI = 2
1 1 1 1
1
January 1, 2023
 Selective Prime Implicant (SPI)
The prime implicants for which each of its minterm is covered by
some essential prime implicant are redundant prime implicants
(RPI). This prime implicant never appears in final solution.

January 1, 2023
 Given F = ∑(1, 5, 6, 7, 11, 12, 13, 15), find
number of implicants, PI, EPI, RPI and
SPI.

January 1, 2023
 Concept of Don’t care

F(0,0) = 1
F(1,1) =F(0,1) = 1

A B F
0 0 1
0 1 1
1 0 X( 0 or 1)
1 1 1

January 1, 2023
 Karnaugh Maps with Don't Care Conditions
In digital circuits,
F(A,B, C) =∑ m( 2, 3, 4, 5 ) +d `(6, 7)
. sometimes we do not care
BC A` B` A` B AB A B` about the output value of a
A 00 01 11 10 combinational logic circuit.
1 1 These conditions denote
A` 0
A 1 1 1 X X the set of inputs that never
occurs for given digital
circuits.
To make a group of cells,
Don’t care = X or d we can use the "don't care"
cells as either 0 or 1, and if
0 1 required, we can also ignore
that cell.
BC B`C` B`C BC B C` BC B`C` B`C BC B C`
A 00 01 11 10 A 00 01 11 10
A` 0 V
1 1 A` 0 1 1
A 1 1 1 1 1 A 1 1 1 0 0

F (A,B,C) = A + B F (A,B,C) = A` B+ AB`

January 1, 2023
 Karnaugh Maps with Don't Care Conditions

F(A,B, C) =∑ m( 1, 2, 4, 5 ) +d (0) ` F(A,B,C D ) =∑ m( 5, 7, 12, 15 ) +d (3, 4, 9, 14)

.
B` C` B` C BC` BC CD C`D` C` D CD C D`
00 01 10 11 AB 00 01 11 10
X 1 1 A`B` 00 x
A` 0
A 1 1 1 A`B 01 x 1 1
AB 11 1 1 x
x
Don’t care = X or d AB` 10

F (A,B,C,D) = A`BC`+A`CD+BD+AC`D+ABC
0 1

BC B`C` B`C BC B C` BC B`C` B`C BC B C`

A 00 01 11 10 A 00 01 11 10
A` 0 V
1 1 1 A` 0 0 1 1
A 1 1 1 A 1 1 1 0 0
F (A,B,C) = B` + A`C` F (A,B,C) = A B`+B`C`+ A`BC`

January 1, 2023
 Quine Mcluskey Method (Tabular Method)
F(A, B, C, D) = ∑ m(0, 1, 3, 7, 8, 9 , 11, 15)

Group Minterm ABCD Group Matched ABCD

D Index A B C D
pair
0 m0 0000
0 m0 0 0 0 0 0 m0 - m 1 000-
1 m1 0001 m0 -m8 -000
1 m1 0 0 0 1
m8 1000 1 m1- m3 00-1
3 m3 0 0 1 1
2 m3 0 011 m1 – m 9 -001
7 m7 0 1 1 1
m8- m 9 100-
8 m8 1 0 0 0
m9 1001
3 m7 0111 2 m3 -m7 0–11
9 m9 1 0 0 1
m3 -m11 - 0 11
11 m11 1 0 1 1 m11 1011 10-1
m9 - m11
15 m15 1 1 1 1 4 m15 1111
3 m7 -m15 - 111
m11- m15 1-11
Note
A` B` C`.D`
Step-1: Write ascending order min term(Index) Ex. 0 0 0 0 A` B` C` D
Step-2: Perform grouping on no. of 1`s
Step-3: Compare nth group with (n+1)th group to obtain match pair (A` B` C`(D+D`)
(Differ by 1 bit only)
0001 = A` B` C` 1
= A` B` C` _
January 1, 2023
 Cont…

Group Matched ABCD Group Matched pair ABCD

pair 0 m0 - m1 –m8 –m9 -00-
0 m0 - m 1 000-
-00- B`C`
m0 -m8 -000 m0 – m8 –m1 –m9
1 m1- m 3 00-1 1 m1- m3 –m9 –m11 -0-1 B`D
m1 – m 9 -001
m8- m9 100- m1 – m9 m3- m11 -0-1
2 m3 -m7 0–11 2 m3- m7 –m11 –m15 --11
- 0 11 CD
m3 -m11
m9 - m11 10-1 m3- m11 –m7 –m15 - - 11
3 m7 -m15 - 111
m11- m15 1-11 B`C`, B`D and CD are called as prime Implicants

000-
Note
100-
January 1, 2023
 Cont…

Group Matched pair ABCD PI Min Min terms

terms
involv 0 1 3 7 8 9 11 15
0 m0 - m1 –m8 –m9 -00- ed
B`C`
m0 – m8 –m1 –m9 -00-
B`C X X X X
0, 1, 8,
1 m1- m3 –m9 –m11 -0-1 `
B`D 9

-0-1 B`D X X X X
m1 – m9 m3- m11 1, 3, 9,

11
2 m3- m7 –m11 –m15 --11
CD
CD X X X X
m3- m11 –m7 –m15 - - 11 3, 7, 11,

15

Prime Implicants(PI) = B`C`, B`D , CD

Essential prime Implicants( EPI) = B`C`, CD

F(A, B, C, D) = B`C+CD

January 1, 2023
 Verification using K-Map
F(A, B, C, D) = ∑ m(0, 1, 3, 7, 8,9, 11, 15)

CD C`D` C`D CD CD`

AB 00 01 11 10

A`B` 00 1 1 1

1
A`B 01

1
AB 11

1 1 1
AB` 10

F(A, B, C, D) = B`C`+CD

January 1, 2023
 Quine Mcluskey Method (tabular Method)
F(A, B, C, D) = ∑ m( 2, 6, 10, 14)

Group Minterm ABCD Group Matched ABCD

D Index A B C D
pair
1 m2 0010
2 m2 0 0 1 0 1 m2- m6 0–10
2 m6 0 110 m2 – m10 -010
6 m6 0 1 1 0
m10 1010 2 m6 –m14 -110
10 m10 1 0 1 0
3 m14 1110 m10 –m14 1–10
14 m14 1 1 1 0

Group Matched pair ABCD Group Matched pair ABCD

1 m2- m6 –m10 – --10 1 m2- m6 –m10 – --10

m14 m14
2 m2 –m10-m6 – --10
m14

January 1, 2023
 Quine Mcluskey Method

PI Min Min term

Group Matche ABCD terms
involved 2 6 10 14
d pair
1 m 2 - m6 --10
CD` CD` 2, 6, X X X X
–m10 –
10, 14
m14
B`D F(A, B, C, D) = CD`

Prime Implicants(PI) = CD`

Essential prime Implicants( EPI) = CD`

January 1, 2023
 Variable and Pairing in K-map

F (A, B) = Pairing possible = 4 Produce = 0 variable Ex. F = 1

=2 Produce = 1 variable Ex. F = A
=1 Produce = 2 variable Ex. F = AB

F (A, B, C) = Pairing possible = 8 Produce = 0 variable Ex. F=1

=4 Produce = 1 variable Ex. F=A
=2 Produce = 2 variable Ex. F = AB
=1 Produce = 3 variable Ex. F = ABC

F (A, B, C, D) = Pairing possible = 16 Produce = 0 variable Ex. F = 1

=8 Produce = 1 variable Ex. F = A
=4 Produce = 2 variable Ex. F = AB
=2 Produce = 3 variable Ex. F = ABC
=1 Produce = 4 variable Ex. F = ABCD

January 1, 2023
Digital Systems
(18B11EC213)
Lect-11
 Digital circuits
Combinational circuits:
Present output is only depend on present input
No feed back
No memory
Examples
Half adder, Full adder, Half subtractor, Full ubtractor, Encoder,
Decoder, Comparator etc
Sequential logic circuits:
Present output is only depend on present input and previous
input
 feed back
 memory
Examples
Flipflop(FF), Registers and counters etc

January 1, 2023
 Half Adder
Procedure to Design:
Identify Input and Output.
Construct truth table.
Write logical expression in SOP and POS form.
Minimize logical expression if possible.
Implements logic circuits.

= A ⊕B

= A.B

Logical expression:

Sum = A`B+AB` = A ⊕B
= ∑ m(1, 2 )

Carry = AB = ∑ m( 3)
January 1, 2023
 Full Adder

Logical expression: Note Cin = C

Sum = A`B`C+A`BC`+AB`C`+ABC = A ⊕B ⊕C

= ∑ m(1, 2, 4, 7 )

Carry = A`BC+AB`C+ABC`+ABC
= A.B+B.C+C.A
= ∑ m( 3, 5, 6, 7)

January 1, 2023
 Half Subtractor
Procedure to Design:
Identify Input and Output.
Construct truth table.
Write logical expression in SOP and POS form.
Minimize logical expression if possible.
Implements logic circuits.

D = A ⊕B
Logical expression:

Difference (D) = A`B+AB` = A ⊕B BO= A.B

= ∑ m(1, 2 )

Borrow (Bo)= A`B = ∑ m( 1)

January 1, 2023
 Full Subtractor

Logical expression:

Difference (D) = A`B`C+A`BC`+AB`C`+ABC

= A ⊕Bin ⊕C Note Bin = C

= ∑ m(1, 2, 4, 7 )

Bo = A`B`C+A`BC`+A`BC`+ABC
= A`B + BC + CA`
= ∑ m( 1, 2 , 3, 7)

January 1, 2023
 Difference between Half adder and full adder 

Half Adder Full Adder

Half Adder is combinational logic circuit Full adder is combinational logical circuit
which adds two 1-bit digits. The half that performs an addition operation on
adder produces a sum of the two inputs. three one-bit binary numbers. The full
adder produces a sum of the three
inputs and carry value.
In Half adder there are two input bits In full adder there are three input bits
( A, B). (A, B, C-in).
Logical Expression for half adder is : Logical Expression for Full adder is :
S=a⊕b ; C=a*b. S=a⊕b⊕Cin; Cout=(a*b)+(Cin*(a⊕b)).
It consists of one EX-OR gate and one It consists of two EX-OR, two AND gate
AND gate. and one OR gate.
It is used in Calculators, computers, It is used in Multiple bit addition, digital
digital measuring devices etc. processors etc.

January 1, 2023
   Multiplexer :
Multiplexer is a data selector which takes several inputs and gives a single output.
In multiplexer we have 2n input lines and 1 output lines where n is the number of selection
lines.

Multiplexer Types
Multiplexers are classified into four types:
2-1 multiplexer ( 1select line)
4-1 multiplexer (2 select lines)
8-1 multiplexer(3 select lines)
16-1 multiplexer (4 select lines)

January 1, 2023
   Demultiplexer :

Demultiplexer is a data distributor which takes a single input and gives several outputs.
In demultiplexer we have 1 input and 2n output lines where n is the selection line.

Types of De multiplexer
De-multiplexers are classified into four types
1-2 demultiplexer (1 select line)
1-4 demultiplexer (2 select lines)
1-8 demultiplexer (3 select lines)
1-16 demultiplexer (4 select lines)
January 1, 2023
 Multiplexer Demultiplexer

Demultiplexer receives digital information

Multiplexer processes the digital information
from a single source and converts it into
from various sources into a single source.
several sources

It is known as Data Selector It is known as Data Distributor

Multiplexer is a digital switch Demultiplexer is a digital circuit

It follows combinational logic type It also follows combinational logic type

It has n data input It has single data input

It has a single data output It has n data outputs

It works on many to one operational principle It works on one to many operational principle

In time division Multiplexing, multiplexer is In time division Multiplexing, demultiplexer

used at the transmitter end is used at the receiver end

January 1, 2023
 2x1 Multiplexer
2x1 Multiplexer has two data inputs I0 & I1, one selection line s0 and one output Y.

The block diagram of 2x1 Multiplexer is shown in the following figure.

Selection Output
Lines
S0 Y
0 I0
1 I1

From Truth table, we can directly write the Boolean function for output,

Y as Y = S0′ I0+S0 I1

January 1, 2023
 Cont..

We can implement this Boolean function using Inverters, AND gates & OR gate.

The circuit diagram of 2x1 multiplexer is shown in the following figure.

January 1, 2023
 4x1 Multiplexer
4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one
output Y. The block diagram of 4x1 Multiplexer is shown in the following figure.

Selection Lines Output

S1 S0 Y
0 0 I0

0 1 I1

1 0 I2

1 1 I3

From Truth table, we can directly write the Boolean function for output,

Y as Y = S1′ S0′ I0+S1′ S0 I1+S1 S0′ I2+S1 S0 I3

January 1, 2023
 Cont..
We can implement this Boolean function using Inverters, AND gates & OR gate.
The circuit diagram of 4x1 multiplexer is shown in the following figure.

January 1, 2023
 Cont..
Analysis of the 4-1 Multiplexer
( s1=0 and s0=0 )
0

January 1, 2023
 Cont..

0
1
1
0
0
1

1
0

0
0

January 1, 2023
 Cont..

0
1 Io
1
0
0 0
1

1 0
0

0 0
0

January 1, 2023
 Cont..

0
1 Io
1
0
0 0
1 Io

1 0
0

0 0
0

January 1, 2023
 Cont..
Analysis of the 4-1 Multiplexer
( s1=0 and s0=1 )

1
0 0
0 1

1 I1
1 I1
0
0
0

1 0
0
January 1, 2023
 Cont..
Analysis of the 4-1 Multiplexer
( s1=1 and s0=0 )

0
1 0
1 0

0 0
0 I2
1 I2
1

0 0
1
January 1, 2023
 Cont..
Analysis of the 4-1 Multiplexer
( s1=1 and s0=0 )

1
0 0
1 0

1 0
0 I3
0 0
1

1 I3
1
January 1, 2023
 8X1 Multiplexer

January 1, 2023
 Implementation of Higher order MUX using lower
order MUX
4 : 1 MUX using 2 : 1 MUX

Number of 2:1 MUX required to implement 4 : 1 MUX is Three(3) 

January 1, 2023
 Implementation of Higher order MUX using lower
order MUX
Implement 8 : 1 MUX using 4 : 1 MUX and 2 : 1 MUX

Number of 4:1 MUX required is Two (2)  Selection Lines Output

Number of 2:1 MUX required is One (1) S2 S1 S0 Y

0 0 0 I0

0 0 1 I1
0 1 0 I2

0 1 1 I3

1 0 0 I4

1 0 1 I5

1 1 0 I6

1 1 1 I7

January 1, 2023
 Implementation of Higher order MUX using lower
order MUX
Implement 8 : 1 MUX using 4 : 1 MUX and OR gate
The cascading of two 4-to-1 multiplexer results
Number of 4:1 MUX required is Two (2) 
in the 8-to-1 multiplexer as shown in the figure
Number of OR gate required is One (1)
There are 8 data inputs that are I0 to I7.

The select inputs S0 and S1 of both the 4-to-1

multiplexers are connected in parallel whereas
the third select input S2 is used for enabling one
multiplexer at a time.

Select input S2 is connected directly to the

Enable (E) terminal of MUX-1 whereas S2- is
connected to the enable terminal of MUX-2.

The output of both the multiplexers is

connected to the OR gate to obtain the final
output Y.
January 1, 2023
 Implementation of logic gates using Mux
Multiplexer can act as universal combinational circuit. All the standard logic gates can be
implemented with multiplexers.

Examples
a) Implementation of NOT gate using 2 : 1 Mux

January 1, 2023
 Cont..
b) Implementation of AND gate using 2 : 1 Mux

c) Implementation of OR gate using 2 : 1 Mux

January 1, 2023
 Cont..
Implementation of NAND, NOR, XOR and XNOR gates requires two 2:1 Mux.

First multiplexer will act as NOT gate which will provide complemented input to the
second multiplexer. 
Input Output
d) Implementation of NAND gate using 2 : 1 Mux
X Y f
0 0 1

0 1 1 f=1

1 0 1

1 1 0 f = Y’

January 1, 2023
 Cont..
e) Implementation of NOR gate using 2 : 1 Mux Input Output
X Y f
0 0 1 f = Y’

0 1 0

1 0 0

1 1 0 f=0

f) Implementation of EX-OR gate using 2 : 1 Mux Input Output

X Y f
0 0 0 f=Y

0 1 1

1 0 1

1 1 0 f = y’

January 1, 2023
 Cont..
g) Implementation of EX-NOR gate using 2 : 1 Mux
Input Output
X Y f
0 0 1 f = Y’

0 1 0

1 0 0

1 1 1 f=y

January 1, 2023
 Implementation of Logic gates using 4: 1 Mux
a) Implementation of AND gate using 4: 1 Mux
Input Output
X Y f
0 0 0

0 1 0

1 0 0

1 1 1

January 1, 2023
 Implementation of Logic gates using 4: 1 Mux
a) Implementation of OR gate using 4: 1 Mux
Input Output
X Y f
0 0 0

0 1 1

1 0 1

1 1 1

January 1, 2023
 Implementation of Boolean function using MUX
 The boolean may be Implement using 2n x 1 MUX

 For n variable boolean function we take n-1 variables as select lines

 The remaining single variable (MSB) of the function is used for input of the Multiplexer

 Now form the implementation table

 First row lists all those minterms where input variable is complemented (say 0)

 Second row lists all those minterms where input variable is in its normal form (say 1)

 Minterms are circled as per given boolean function.

 Use these following steps to find multiplexer inputs

 If the 2 minterms in a column are not circled, 0 is placed on the corresponding

multiplexers input

January 1, 2023
 Implementation of Boolean function using MUX
 If the 2 minterms in a column are not circled, 1 is placed on the corresponding
multiplexers input

 If the minterms in a first row is circled and not the second row , apply first row of the
variable to the corresponding multiplexers input

 If the minterms in a second row is circled and not the first row , apply second row of
the variable to the corresponding multiplexers input

January 1, 2023
 Implementation of Boolean function using MUX

January 1, 2023
 Cont..
A is MSB and D is LSB

January 1, 2023
 Cont..
2) Example

January 1, 2023
 Cont..
3) Example

1 0
0 1
1 2
0 3
0 4 8:1 MUX F
0 5
1 6
1 7
S2 S1 S0

A B C

January 1, 2023
 Cont..
3) Example
Implement given SOP function f(A, B, C) = m(0, 1, 4, 6, 7) using 4x1 MUX

A, B are considered as selection inputs and C as data input

January 1, 2023
 Cont..

Implementation table 4x1 Mux Implementation

A, B selection inputs

January 1, 2023
 Demultiplexer
1x2 Demultiplexer

January 1, 2023
 Demultiplexer

January 1, 2023
 Demultiplexer

January 1, 2023
 Demultiplexer

January 1, 2023
 Implementation of Higher order Demultiplexer
using lower order Demultiplexer
1x8 De-Multiplexer
let us implement 1x8 De-Multiplexer using 1x4 De-multiplexers and 1x2 De-Multiplexer.

We know that 1x4 De-Multiplexer has single input, two selection lines and four outputs.
Whereas, 1x8 De-Multiplexer has single input, three selection lines and eight outputs

So, we require two 1x4 De-Multiplexers in second stage in order to get the final eight
outputs.

Since, the number of inputs in second stage is two, we require 1x2 DeMultiplexer in first
stage so that the outputs of first stage will be the inputs of second stage.

Input of this 1x2 De-Multiplexer will be the overall input of 1x8 De-Multiplexer

Let the 1x8 De-Multiplexer has one input I, three selection lines s 2, s1 & s0 and outputs Y7 to
Y0. The Truth table of 1x8 De-Multiplexer is shown below
January 1, 2023
 Implementation of Higher order Demultiplexer
using lower order Demultiplexer

January 1, 2023
 Implementation of Higher order Demultiplexer
using lower order Demultiplexer
We can implement 1x8 De-Multiplexer using lower order Multiplexers easily by considering
the above Truth table. The block diagram of 1x8 De-Multiplexer is shown in the following
figure.

January 1, 2023
 Implementation of Higher order Demultiplexer
using lower order Demultiplexer
The common selection lines, s1 & s0 are applied to both 1x4 De-Multiplexers.

The outputs of upper 1x4 De-Multiplexer are Y7 to Y4 and the outputs of lower 1x4 De-
Multiplexer are Y3 to Y0.

The other selection line, s2 is applied to 1x2 De-Multiplexer.

If s2 is zero, then one of the four outputs of lower 1x4 De-Multiplexer will be equal to
input, I based on the values of selection lines s1 & s0.

Similarly, if s2 is one, then one of the four outputs of upper 1x4 DeMultiplexer will be
equal to input, I based on the values of selection lines s 1 & s0.

January 1, 2023
 Implementation of Higher order Demultiplexer
using lower order Demultiplexer
The common selection lines, s1 & s0 are applied to both 1x4 De-Multiplexers.

The outputs of upper 1x4 De-Multiplexer are Y7 to Y4 and the outputs of lower 1x4 De-
Multiplexer are Y3 to Y0.

The other selection line, s2 is applied to 1x2 De-Multiplexer.

If s2 is zero, then one of the four outputs of lower 1x4 De-Multiplexer will be equal to
input, I based on the values of selection lines s1 & s0.

Similarly, if s2 is one, then one of the four outputs of upper 1x4 DeMultiplexer will be
equal to input, I based on the values of selection lines s 1 & s0.

January 1, 2023
 Implementation of Higher order Demultiplexer
using lower order Demultiplexer
1x16 De-Multiplexer
Let the 1x16 De-Multiplexer has one input I, four selection lines s 3, s2, s1 & s0 and outputs
Y15 to Y0. The block diagram of 1x16 De-Multiplexer using lower order Multiplexers is
shown in the following figure.

January 1, 2023
 Implementation of Higher order Demultiplexer
using lower order Demultiplexer

The common selection lines s2, s1 & s0 are applied to both 1x8 De-Multiplexers.

The outputs of upper 1x8 De-Multiplexer are Y15 to Y8 and the outputs of lower 1x8
DeMultiplexer are Y7 to Y0.

The other selection line, s3 is applied to 1x2 De-Multiplexer.

If s3 is zero, then one of the eight outputs of lower 1x8 De-Multiplexer will be equal to
input, I based on the values of selection lines s2, s1 & s0.

Similarly, if s3 is one, then one of the 8 outputs of upper 1x8 De-Multiplexer will be equal
to input, I based on the values of selection lines s2, s1 & s0

January 1, 2023
 Implementation of Higher order Demultiplexer
using lower order Demultiplexer

The common selection lines s2, s1 & s0 are applied to both 1x8 De-Multiplexers.

The outputs of upper 1x8 De-Multiplexer are Y15 to Y8 and the outputs of lower 1x8
DeMultiplexer are Y7 to Y0.

The other selection line, s3 is applied to 1x2 De-Multiplexer.

If s3 is zero, then one of the eight outputs of lower 1x8 De-Multiplexer will be equal to
input, I based on the values of selection lines s2, s1 & s0.

Similarly, if s3 is one, then one of the 8 outputs of upper 1x8 De-Multiplexer will be equal
to input, I based on the values of selection lines s2, s1 & s0

January 1, 2023
 Encoder
An Encoder is a combinational circuit that performs the reverse operation of Decoder.

It has maximum of 2^n input lines and ‘n’ output lines, hence it encodes the information
from 2^n inputs into an n-bit code.

It will produce a binary code equivalent to the input, which is active High. Therefore, the
encoder encodes 2^n input lines with ‘n’ bits

January 1, 2023
 Encoder
Types of Encoder

January 1, 2023
 Encoder
4 to 2 line Encoder:

In 4 to 2 line encoder, there are total of four inputs, i.e., Y 0, Y1, Y2, and Y3, and two outputs,
i.e., A0 and A1.

In 4-input lines, one input-line is set to true at a time to get the respective binary code in the
output side.

The block diagram and the truth table of the 4 to 2 line encoder.

January 1, 2023
 Encoder

January 1, 2023
 Encoder
8 to 3 Encoder:
The 8 to 3 line Encoder is also known as Octal to Binary Encoder.

In 8 to 3 line encoder, there is a total of eight inputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and
Y7 and three outputs, i.e., A0, A1, and A2.

In 8-input lines, one input-line is set to true at a time to get the respective binary code in
the output side.

Below are the block diagram and the truth table of the 8 to 3 line encoder.

January 1, 2023
 Encoder

January 1, 2023
 Encoder Design Issues
There are two ambiguities associated with the design of a simple
encoder:

1. Only one input can be active at any given time. If two

inputs are active simultaneously, the output produces an
undefined combination (for example, if D3 and D6 are 1
simultaneously, the output of the encoder will be 111).

2. An output with all 0's can be generated when all the inputs
are 0's,or when D0 is equal to 1.

January 1, 2023
 Priority Encoders
Solves the ambiguities mentioned above.

Multiple asserted inputs are allowed; one has priority over all others.

Separate indication of no asserted inputs.

January 1, 2023
 4-to-2 Priority Encoder (cont.)

January 1, 2023
 4-to-2 Priority Encoder (cont.)

The operation of the priority encoder is such that:

If two or more inputs are equal to 1 at the same time, the input in the
highest-numbered position will take precedence.

A valid output indicator, designated by V, is set to 1 only when one

or more inputs are equal to 1.

V = D3 + D2 + D1 + D0 by inspection.

January 1, 2023
 4-to-2 Priority Encoder (cont.)

This Priority encoder consists of 4 inputs and three outputs.

Although an encoder has 2n inputs and n outputs, it has a third output ‘V’ which is
a valid bit indicator and is set to one when one or more inputs are active or equal to
1

This valid bit is zero when all the inputs are zero which indicates that there is no
valid input. On this condition, other outputs are considered as don’t care conditions
and are not inspected when V is zero.

In the truth table, D3 has the highest priority and D0 has lowest priority. When D3
is active or 1, then regardless of other inputs, the output is 11. The next higher
priority is D2 after D3

The next higher priority is D2 after that D1. Thus, when D3 is 0 and D2 is 1 then
regardless of other two inputs (which has lower priority), the output is 10.

When higher priority inputs are zero then the output for D1 is generated and so on
down the priority levels
January 1, 2023
 4-to-2 Priority Encoder K-Maps

January 1, 2023
 4-to-2 Priority Encoder Logic Diagram

January 1, 2023
 Decoder

January 1, 2023
 2x4 decoder

January 1, 2023
 3x8 decoder

January 1, 2023
 Implementing Full Adder using 3x8 Decoder

S(X,Y,Z) = SUM m(1,2,4,7)

C(X,Y,Z) = SUM m(3,5,6,7)

January 1, 2023
 Implementation of Higher-order Decoders
3 to 8 Decoder using 2x4 decoder

We know that 2 to 4 Decoder has two inputs, A1 & A0 and four outputs, Y3 to Y0.

Whereas, 3 to 8 Decoder has three inputs A2, A1 & A0 and eight outputs, Y7 to Y0

We can find the number of lower order decoders required for implementing higher order
decoder using the following formula

Where,
m1 is the number of outputs of lower order decoder.
m2 is the number of outputs of higher order decoder.
Here, m1 = 4 and m2 = 8. Substitute, these two values in the above formula.
January 1, 2023
 3 to 8 Decoder using 2x4 decoder (cont..)
Therefore, we require two 2 to 4 decoders for implementing one 3
to 8 decoder. The block diagram of 3 to 8 decoder using 2 to 4
decoders is shown in the following figure.

January 1, 2023
 3 to 8 Decoder using 2x4 decoder (cont..)
The parallel inputs A1 & A0 are applied to each 2 to 4 decoder.

The complement of input A2 is connected to Enable, E of lower 2 to 4 decoder in order

to get the outputs, Y3 to Y0.

These are the lower four min terms.

The input, A2 is directly connected to Enable, E of upper 2 to 4 decoder in order to get
the outputs, Y7 to Y4. These are the higher four min terms

January 1, 2023
 4 to 16 decoder using 3 to 8 decoders

January 1, 2023
 4 to 16 decoder using 3 to 8 decoders

The parallel inputs A2, A1 & A0 are applied to each 3 to 8 decoder. The complement of input,
A3 is connected to Enable, E of lower 3 to 8 decoder in order to get the outputs, Y 7 to Y0.
These are the lower eight min terms. The input, A3 is directly connected to Enable, E of
upper 3 to 8 decoder in order to get the outputs, Y 15 to Y8. These are the higher eight min
terms.
January 1, 2023
 4 to 16 decoder using 2 to 4 decoders

January 1, 2023
 SEQUENTIAL CIRCUITS

A combinational logic circuit is a circuit whose output depends only on the

circuit’s present inputs. (“Has no memory of the past.”)

A sequential logic circuit is a circuit whose output may depend on the

circuit’s previous states as well as its present inputs. (“Has a memory.”)

January 1, 2023
 SEQUENTIAL CIRCUITS
The current state is “held” in memory and the next state is
computed based the current state and the current inputs

In a synchronous systems, the clock controls the sequence of

events

Latches are basic storage elements that operate with signal levels
(rather than signal transitions).

Latches are level-sensitive devices.

Latches are useful for the design of the asynchronous sequential

circuit.

Latches controlled by a clock are flip-flops

January 1, 2023
 SEQUENTIAL CIRCUITS
The latches and flip flops are the building blocks of sequential
circuits

Latch is a circuit with two stable states

Latch is a temporary storage device.

Latch has two inputs and two outputs.

Latch outputs are always complement of each other.

A latch does not have a clock signal.

January 1, 2023
 SEQUENTIAL CIRCUITS
SR latch

The basic storage element.

There are two inputs R (RESET) and S (SET)

There are Two outputs Q and Q’

Where Q is never equal to Q’ and both are complement of each other.

If Q=1 the condition is set

If Q=0 he condition is reset

January 1, 2023
 SEQUENTIAL CIRCUITS

SR (Set-Reset) Latch – SR Latch circuit can be implemented with:

(i) 2 cross-coupled NOR gate or 2 cross-coupled NAND gate.
(ii) 2 input (S for SET and R for RESET).
(iii) 2 output Q and Q’

January 1, 2023
 SEQUENTIAL CIRCUITS

SR Latch (NAND gates)

The two NAND gates are cross-coupled so that output of NAND-1 is

connected to one of the inputs of NAND-2, and vice versa.

The gate outputs are labeled Q and Q’

Under normal operating conditions, these outputs are always

complement of each other.

There are two inputs

SET input is the input that sets Q to the 1 state
RESET input is the input that resets Q to the 0 state

January 1, 2023
 SR Latch (NAND gates) cont…

 The SET and RESET inputs are normally resting in HIGH state.

One of them will be pulsed LOW when ever we want to change the
latch outputs

Analysis ( Let us consider S = R =1)

There are two possibilities for the output when S = R =1

First possibility (Q =1 , Q’=0 )

Second possibility (Q =0 , Q’=1 )

January 1, 2023
 SR Latch (NAND gates) cont…

(a) Logic diagram (b) Functional table

January 1, 2023
 SR Latch (NAND gates) cont…
 These possible combinations are represented in fig(a) and fig(b)

January 1, 2023
 SR Latch (NAND gates) cont…
 S = R =1 :This condition is the normal resting state and it has no effect on the
output state. (i.e. The outputs Q and Q’ will remain in whatever state they were in
prior to this input condition).

 S = 0, R =1 : This condition will always cause the output to go to Q=1 state.

This condition is also called as setting the latch.

 S = 1, R =0 : This condition will always produce the Q=0 state. This condition
is also called as resetting the latch.

 S = 0, R =0 : This condition tries to set and reset the latch at the same time and
can produce ambiguous results. This condition is not used.

January 1, 2023
 SR Latch (NOR gates)
 The Two cross - coupled NOR gates can be used as a NOR gate latch.

 The structure is similar to NAND latch except that the Q and Q’ outputs are
reversed positions.

 The NOR gate latch , truth table and simplified block diagram is shown below

January 1, 2023
 SR Latch (NOR gates) cont…
 S = 0, R =0 : This condition is the normal resting state for NOR latch and it has
no effect on the output state. (i.e. The outputs Q and Q’ will remain in whatever
state they were in prior to this input condition).

 S = 1, R =0 : This condition will always set Q = 1 state. This

condition is also called as setting the latch.

 S = 0, R =1 : This condition will always reset Q = 0 state. This

condition is also called as resetting the latch

 S = 1, R =1 : This condition tries to set and reset the latch at the

same time and can produce ambiguous results (Q = Q’ = 0). This
condition is not used.

January 1, 2023
 Clock Signals and Clocked Flip Flops
 In synchronous systems, the exact times at which any output can change states
are determined by a signal commonly called as clock.

 This clock signal is generally a rectangular pulse train or a square wave as

shown in figure

 Clock Signals.

January 1, 2023
 Clock Signals and Clocked Flip Flops

Positive and Negative Edge triggered Clocks

January 1, 2023
 Clock Signals and Clocked Flip Flops

SR Flip-Flop

January 1, 2023
 Clock Signals and Clocked Flip Flops

SR Flip-Flop symbolic representation and truth table

January 1, 2023
 Example clocked SR Flip flop

January 1, 2023
 Example clocked SR Flip flop
 The operation of SR Flip flop can be illustrated using the above waveforms

 Initially all the inputs are 0 and the output is assumed to be 0 (Q0 = 0)

 When the positive edge of the first clock pulse occurs (Point a) the S and R inputs
are both 0, so the FF is not affected and remains in the Q=0 state( i.e., Q = Q 0 ).

 At the occurrence of the positive edge of 2nd clock pulse (Point c) the S input is
now high and R input still low, Therefore the FF sets to the 1 State at the rising
edge of this clock pulse.

 When the positive edge of the 3rd clock pulse occurs (Point e) ,it can be noted that
S=0 and R=1 which causes the FF to reset to 0 state.

 The positive edge of the 4th clock pulse sets the FF once again to the Q=1 state
(Point g) because of S=1 and R=0

 The 5th clock pulse finds that S=1 and R=0 during the positive edge of the clock
pulse (Point i). However, Q is already high, so it remains in that state.
January 1, 2023
 Example clocked SR Flip flop
 The S=R=1 condition is not used because it results in ambiguous condition.

 It can be noted that the above waveforms are not affected by the negative edge of
the clock pulse.

January 1, 2023
 Example clocked SR Flip flop
 Reduced truth table.

January 1, 2023
 Example clocked SR Flip flop
 Characteristics equation.

January 1, 2023
 Example clocked SR Flip flop
 For a given combination of present state Qn and next state Qn+1, excitation table tell
the inputs required.

January 1, 2023
 Clocked JK Flip flop
 In J-K Flip flop the J and K inputs control the state of the FF in the same
way as the S and R inputs for the SR flip flop .

 The major difference in between these is in JK flip flop the J=K=1

condition does not result in an ambiguous output.

 For the 1,1 condition the FF will always go to its opposite state upon
transition of the clock pulse. This is called as toggle mode of operation.

 In this mode if both J and K are HIGH ,the FF will change states(Toggle)
for the triggering pulse of the clock signal.

January 1, 2023
 Clocked JK Flip flop
 J-K Flip flop

January 1, 2023
 Clocked JK Flip flop
 J-K Flip flop

January 1, 2023
 Clocked JK Flip flop
 Reduced truth table J-K Flip flop

January 1, 2023
 Clocked JK Flip flop
 Characteristics equation

January 1, 2023
 Clocked JK Flip flop
 For a given combination of present state Qn and next state Qn+1, excitation table
tell the inputs required.

January 1, 2023
 Example Clocked JK Flip flop
 J-K Flip flop symbol and truth table

January 1, 2023
 Example Clocked JK Flip flop
 The operation of JK Flip flop can be illustrated using the above waveforms

 Initially all the inputs are 0 and the output is assumed to be 1 (Q0 = 1)

 When the positive edge of the first clock pulse occurs (Point a) the J=0 and K=1
condition exists, so the FF will be cleared to Q=0 state

 The occurrence of the positive edge of 2nd clock pulse (Point c) finds J=K=1 This
causes the FF to toggle to its opposite state, Q = 1.

 When the positive edge of the 3rd clock pulse occurs (Point e), finds J=K=0 so the
FF does not change states on this transitions.

 The positive edge of the 4th clock pulse sets the FF to the Q=1 state (Point g)
because of J=1 and K=0

 The 5th clock pulse finds that J=1 and K=1 during the positive edge of the clock
pulse (Point i). The FF toggles to its opposite state. The same thing occurs at point
K
January 1, 2023
 Race around condition in JK Flip flop
 The change of output more than once within one CLK pulse is called as race
around condition.

 The inherent difficulty of an S-R flip-flop (i.e., S = R = 1) is eliminated by using

the feedback connections from the outputs to the inputs of gate 1 and gate 2 as
discussed in JK flip-flop.

 Truth tables JK flip-flop were formed with the assumption that the inputs do not
change during the clock pulse (CLK = 1). But the consideration is not true
because of the feedback connections.

 Consider, for example, that the inputs are J = K = 1 and Q = 1, and a pulse as
shown in Figure below is applied at the clock input.

January 1, 2023
 Race around condition in JK Flip flop
Consider, for example, that the inputs are J = K = 1 and Q = 1, and a pulse as
shown above is applied at the clock input.

After a time interval Δt equal to the propagation delay through two NAND
gates in series, the outputs will change to Q = 0. So now we have J = K = 1 and
Q=0. After another time interval of Δt the output will change back to Q = 1.

Hence, we conclude that for the time duration of tp of the clock pulse, the
output will oscillate between 0 and 1.

Hence, at the end of the clock pulse, the value of the output is not certain. This
situation is referred to as a race-around condition

January 1, 2023
 Race around condition in JK Flip flop
Generally, the propagation delay of TTL gates is of the order of nanoseconds.
So if the clock pulse is of the order of microseconds, then the output will
change thousands of times within the clock pulse.

This race-around condition can be avoided if tp < Δt < T.

Due to the small propagation delay of the ICs it may be difficult to satisfy the
above condition.

A more practical way to avoid the problem is to use the master-slave (M-S)
configuration as discussed below.

January 1, 2023
 Master slave JK Flip Flop

 Race Around Condition in JK Flip-flop: For J-K flip-flop, if J =

K=1, and if CLK = 1 for a long period of time, then Q output will
toggle as long as CLK is high, which makes the output of the flip-
flop unstable or uncertain.

 This problem is called race around condition in J-K flip-flop.

 This problem (Race Around Condition) can be avoided by ensuring

that the clock input is at logic “1” only for a very short time.

 This introduced the concept of Master Slave JK flip flop.

January 1, 2023
 Master slave JK Flip Flop
Master Slave JK Flip Flop :
The Master-Slave Flip-Flop is basically a combination of two JK flip-
flops connected together in a series configuration.

Out of these, one acts as the “master” and the other as a “slave”.

The output from the master flip flop is connected to the two inputs of the
slave flip flop whose output is fed back to inputs of the master flip flop.

In addition to these two flip-flops, the circuit also includes an inverter.

The inverter is connected to clock pulse in such a way that the inverted
clock pulse is given to the slave flip-flop.

In other words if CLK=0 for a master flip-flop, then CLK=1 for a slave
flip-flop and if CLK=1 for master flip flop then it becomes 0 for slave
flip flop.
January 1, 2023
 Master slave JK Flip Flop
 The first flip-flop is called the master, and it is driven by the
positive clock cycle.

 The second flip-flop is called the slave, and it is driven by the

negative clock cycle.

 During the positive clock cycle, master flip-flop gives the

intermediate output but slave flip-flop will not give the final
output.

 During the negative clock cycle, slave flip-flop gets activated

and copies the previous output of the master flip-flop and
produces the final output.

January 1, 2023
 Master slave JK Flip Flop
 The first flip-flop is called the master, and it is driven by the
positive clock cycle.

January 1, 2023
 Master slave JK Flip Flop
 Master-slave JK flip-flop constructed by using NAND gates

January 1, 2023
 Master slave JK Flip Flop
 Master-slave JK flip-flop working
 When the clock pulse goes to 1, the slave is isolated; J and K inputs may affect
the state of the system. The slave flip-flop is isolated until the CLK goes to 0.
When the CLK goes back to 0, information is passed from the master flip-flop
to the slave and output is obtained.

 Firstly the master flip flop is positive level triggered and the slave flip flop is
negative level triggered, so the master responds before the slave.

 If J=0 and K=1, the high Q’ output of the master goes to the K input of the slave
and the clock forces the slave to reset, thus the slave copies the master.

 If J=1 and K=0, the high Q output of the master goes to the J input of the slave
and the Negative transition of the clock sets the slave, copying the master.

 If J=1 and K=1, it toggles on the positive transition of the clock and thus the
slave toggles on the negative transition of the clock.

 If J=0 and K=0, the flip flop is disabled and Q remains unchanged.
January 1, 2023
 Master slave JK Flip Flop
 Master-slave JK flip-flop timing diagram

January 1, 2023
 Master slave JK Flip Flop
When the Clock pulse is high the output of master is high and remains
high till the clock is low because the state is stored.

Now the output of master becomes low when the clock pulse becomes
high again and remains low until the clock becomes high again.

Thus toggling takes place for a clock cycle.

When the clock pulse is high, the master is operational but not the slave
thus the output of the slave remains low till the clock remains high.

When the clock is low, the slave becomes operational and remains high
until the clock again becomes low.

Toggling takes place during the whole process since the output is
changing once in a cycle.

January 1, 2023
 Clocked D Flip flop
 Unlike the SR and JK Flip flops ,this FF has only one synchronous control input,
D which stands for data.

Qn+1 = D

January 1, 2023
 Clocked D Flip flop
 Consider a positive edge triggered D-FF as shown in the fig

January 1, 2023
 Clocked D Flip flop
 Assume that Q is initially high .when the first positive edge of the clock
pulse occurs at point a, the D input is low thus Q will go to the 0 state.

 Even though the D input levels changes between the points a and b it has
no effect on Q.

 Q is storing the LOW that was on D at point a. When positive edge of the
clock occurs at point b, Q goes HIGH at that time.

 Q is storing the LOW that was on D at point a. When positive edge of the
clock occurs at point b, Q goes HIGH at that time.

 Q stores this HIGH until the next positive edge of the clock causes Q to go
LOW. Since D is LOW at that time.
 Similarly Q takes on the values present at D the positive edge of the clock
occurs at the points d, e, f and g.

January 1, 2023
 T Flip Flop
In T flip flop, "T" defines the term "Toggle".

we provide only a single input called "Toggle" or "Trigger" input to avoid an

intermediate state occurrence.

January 1, 2023
 T Flip Flop
Operation of T-Flip Flop

The next sate of the T flip flop is similar to the current state when the T
input is set to false or 0.

If toggle input is set to 0 and the present state is also 0, the next state will be
0.

If toggle input is set to 0 and the present state is 1, the next state will be 1.

The next state of the flip flop is opposite to the current state when the toggle
input is set to 1.

If toggle input is set to 1 and the present state is 0, the next state will be 1.

If toggle input is set to 1 and the present state is 1, the next state will be 0.

January 1, 2023
 T Flip Flop
 Generally, T flip flops are not available as ICs. So they can be constructed
by using JK flip – flop and SR flip – flop and D flip – flop. The symbol of T
flip – flop made from JK flip – flop is shown below

 With a slight modification of a J-K flip-flop, we can construct a new flip-

flop called a T flip-flop.

 If the two inputs J and K of a J-K flip-flop are tied together it is referred to
as a T flip-flop. Hence, a T flip-flop has only one input T and two outputs Q
and Q'.

 Since there are only two states, a T flip-flop is a very good option to use in
counter design and in sequential circuits design where switching an
operation is required.

January 1, 2023
 T Flip Flop
The truth table shows that when T = 0, then Qn+1 = Qn, i.e., the next state is
the same as the present state and no change occurs.

When T = 1, then Qn+1 = Q'n, i.e., the state of the flip-flop is complemented.

The truth table of a T flip-flop is given below:

January 1, 2023
 T Flip Flop
Characteristic Table of a T Flip-flop.

The characteristic equation of the T flip-flop from the characteristic table

with the help of the Karnaugh map below:-

January 1, 2023
 T Flip Flop
 Summary of characteristics equations for finding next state from the current
state

January 1, 2023
 Flip Flop Conversions
There are four types of flip-flops, such as:
SR flip – flop
D flip – flop
JK flip – flop
T flip – flop

Among these, the most widely used flip-flops are JK flip-flops and D
flip- flops . And so their availability in the form of integrated circuits
(IC’s) is abundant.

S-R flip – flop and T flip – flop are not available in the market as
integrated circuits (IC’s) (even though a very few number of SR
flip – flops are available as IC’s, they are not frequently used).

However, sometimes S-R and T flip-flops are also required in order to

implement a logic circuit. In such cases, what we can do is to convert
one type of flip-flop into another.
January 1, 2023
 Flip Flop Conversions
The most common types of flip-flop conversions are:
J-K Flip-flop to S-R Flip-flop
J-K Flip-flop to D Flip-flop
J-K Flip-flop to T Flip-flop
S-R Flip-flop to J-K Flip-flop
S-R Flip-flop to D Flip-flop
S-R Flip-flop to T Flip-flop
D Flip-flop to S-R Flip-flop
D Flip-flop to J-K Flip-flop

January 1, 2023
 Flip Flop Conversions
(i) Conversion of J-K Flip-Flop to S-R Flip-Flop
So first we design a combinational circuit with S and R as its inputs and we connect
its output to the input of our available flip flop
step-1: Write the truth table of the Desired flip-flop
Here the desired flip-flop is S-R flip-flop. So we need to write the truth table of the S-
R flip-flop in the first step.

January 1, 2023
 Flip Flop Conversions
Step 2: Obtain the Excitation Table for the given Flip-Flop from
its Truth Table

Truth table for J-K flip-flop Excitation table for J-K flip-flop

January 1, 2023
 Flip Flop Conversions
Step 3: Obtain Conversion Table
The conversion table is obtained by filling-up the values of the J and K inputs
for the given Qn and Qn+1, by referring to the excitation table.

January 1, 2023
 Flip Flop Conversions
Step 4: Simplify the Expressions for the Inputs of the given Flip-Flop
In this step, we will find the logical expressions for the inputs J and K in terms
of S, R and Qn using suitable simplification technique like K-map .

Step 5: Design the Necessary Circuit and make the Connections accordingly

January 1, 2023
 Flip Flop Conversions
(ii) Conversion of JK Flip Flop to D Flip Flop

step-1 : Truth table for D Flip-flop

step-2 : Excitation Table for J-K Flip-flop

January 1, 2023
 Conversion of JK Flip Flop to D Flip Flop
step-3 : Conversion Table

step-4 : k-map Simplification

January 1, 2023
 Conversion of JK Flip Flop to D Flip Flop
step-5 : Circuit Design

January 1, 2023
 Conversion of JK Flip Flop to T Flip Flop
step-1 : Truth table for T Flip-flop step-2 : Excitation Table for J-K Flip-flop

step-3 : Conversion Table

step-4 : k-map Simplification

step-5 : Circuit Design

January 1, 2023
 Conversion of SR Flip Flop to J-K Flip Flop
step-1 : Truth table for JK Flip-flop step-2 : Excitation Table for SR Flip-flop

step-3 : Conversion Table

step-4 : k-map Simplification

step-5 : Circuit Design

January 1, 2023
 Conversion of SR Flip Flop to D Flip Flop
step-1 : Truth table for D Flip-flop step-2 : Excitation Table for SR Flip-flop

step-3 : Conversion Table

step-4 : k-map Simplification

step-5 : Circuit Design

January 1, 2023
 Conversion of SR Flip Flop to T Flip Flop
step-1 : Truth table for T Flip-flop step-2 : Excitation Table for SR Flip-flop

step-3 : Conversion Table

step-4 : k-map Simplification

step-5 : Circuit Design

January 1, 2023
 Conversion of D Flip Flop to J-K Flip Flop
step-1 : Truth table for JK Flip-flop step-2 : Excitation Table for D Flip-flop

step-3 : Conversion Table

step-4 : k-map Simplification

step-5 : Circuit Design

January 1, 2023
January 1, 2023
 Clocked Flip flops with PRESET and CLEAR Inputs

January 1, 2023
 Clocked Flip flops with PRESET and CLEAR Inputs

January 1, 2023
 Clocked Flip flops with PRESET and CLEAR Inputs

January 1, 2023
 Clocked JK Flip flops with PRESET and CLEAR Inputs

January 1, 2023
 Clocked JK Flip flops with PRESET and CLEAR Inputs

January 1, 2023
 Example JK Flip flops with PRESET and CLEAR Inputs

January 1, 2023
 Example JK Flip flops with PRESET and CLEAR Inputs

January 1, 2023
 Example JK Flip flops with PRESET and CLEAR Inputs

January 1, 2023
 Example JK Flip flops with PRESET and CLEAR Inputs

January 1, 2023
 Registers

January 1, 2023