Double-Gate Tunnel FET With High-κ Gate Dielectric

Kathy Boucart and Adrian Mihai Ionescu, Member, IEEE

Copyright © 2007 IEEE. Reprinted from IEEE Transactions on Electron Devices, VOL 54, NO 7, July 2007.

Abstract—In this paper, we propose and validate a novel One such reported device is the Tunnel FET that incorpo-
design for a double-gate tunnel field-effect transistor rates a delta-layer of SiGe at the edge of the p+ region, in
(DG Tunnel FET), for which the simulations show signif- order to reduce the barrier width and, thereby, improve the
icant improvements compared with single-gate devices subthreshold swing and ON-current [10], [11]. Another is the
using an SiO2 gate dielectric. For the first time, DG Tun- carbonnanotube FET, which uses two independently con-
nel FET devices, which are using a high-κ gate dielectric, trolled gates to change the energy bands in the channel [7].
are explored using realistic design parameters, showing
In most of the literature published so far, the experi-
an ON-current as high as 0.23 mA for a gate voltage of
mentally shown ON-currents are unacceptably low for a
1.8 V, an OFF-current of less than 1 fA (neglecting gate
technology that would like to replace the conventional
leakage), an improved average subthreshold swing of 57
MOSFET (hereafter, simply referred to as the MOSFET).
mV/dec, and a minimum point slope of 11 mV/dec. The
While OFF-currents are in the range of femtoamperes [7]
2-D nature of Tunnel FET current flow is studied, dem-
or picoamperes [8], [9], ON-currents for applied drain and
onstrating that the current is not confined to a channel
gate voltages of 2 V are still limited to the nanoamperes
at the gate-dielectric surface. When varying temperature,
range [8], [9]. Furthermore, in order to have a CMOS-com-
Tunnel FETs with a high-κ gate dielectric have a smaller
patible technology, voltages should be limited even more,
threshold voltage shift than those using SiO2, while the
to about 1.2 V. While one publication shows ON-currents
subthreshold slope for fixed values of Vg remains nearly
up to 0.5 mA/µm [13], these devices seem to be hybrid de-
unchanged, in contrast with the traditional MOSFET.
vices rather than pure Tunnel FETs, since their subthresh-
Moreover, an Ion/Ioff ratio of more than 2 × 1011 is shown
old slope is constant rather than Vg-dependent.
for simulated devices with a gate length (over the intrin-
sic region) of 50 nm, which indicates that the Tunnel FET Looking at the 2005 ITRS [15], the Tunnel FET technology
is a promising candidate to achieve better-than-ITRS fits best into the Low Standby Power (LSTP) category. For
low-standby-power switch performance. the 50-nm node, an ON-current of 0.612 mA is required
with an OFF-current of 10 pA. New Tunnel FET designs
Index Terms—Band-to-band tunneling, double gate (DG),
will be needed, in order to attain this Ion without sacrific-
gated p-i-n diode, high-κ dielectric, subthreshold swing,
ing Ioff. The design we present here, a double-gate (DG)
tunnel fieldeffect transistor (FET).
device with a high-κ gate dielectric, is a way of achieving
similar improvements (with an ON-current of 0.23 mA,
I. INTRODUCTION lower than the ITRS requirement, but an OFF-current sig-
AS MOSFETs continue to get smaller and run into funda- nificantly reduced compared to a conventional MOSFET),
mental performance limitations, there is a renewed inter- while taking advantage of the reduced subthreshold
est in exploring devices that use tunneling for their ON- swing possible with this sort of tunneling device. It is im-
current [1]–[14]. In particular, there is a focus on devices portant to notice that the results presented here (notably,
which act as field-effect transistors (FETs), where a change the ON-current) are not identical with those shown in our
of gate voltage turns the current ON and OFF, but which earlier report [21], due to a change in the band-to-band
use band-to-band tunneling in their ON-state, as well as tunneling model. The new results, however, qualitatively
in the transition between the OFF- and ON-states. These confirm all initial findings and orders of magnitude (this
devices have the potential for extremely low OFF-current, will be discussed in detail in Section IV).
and present the possibility to lower the subthreshold
For reasons of cost and compatibility with already-exist-
swing beyond the 60-mV/dec limit of conventional MOS-
ing fabrication technology, a process that uses standard
FETs. Therefore, they seem well adapted to be candidates
CMOS fabrication steps and batch (rather than wafer-by-
for an ultimately scaled quasi-ideal switch.
wafer) processing is preferable. The devices simulated
here have been designed to be compatible with this type
Manuscript received September 13, 2006; revised February 26, of processing, to make integration with CMOS possible
2007. The review of this paper was arranged by Editor C.-Y. Lu. and to keep costs low. The materials can be deposited
The authors are with the Swiss Federal Institute of Technology, with bulk-deposition methods, such as chemical vapor
1015 Lausanne, Switzerland (e-mail: [email protected]). deposition (CVD), rather than expensive techniques,
such as molecular beam epitaxy (MBE).
Digital Object Identifier 10.1109/TED.2007.899389

The Simulation Standard Page 4 January, February, March 2008

 DG device. To operate these devices, the p-i-n
diode is reversebiased —in our simulations, the
source is grounded, and a positive voltage is
applied to the drain—and a voltage is applied
to the gate(s). Without a gate voltage, the width
of the energy barrier between the intrinsic re-
gion and the p+ region is much wider than 10
nm (the approximate minimum for significant
tunneling probability), and the device is in the
OFF-state, as shown in the cross section of the
device in Figure 2(a). As the positive gate volt-
age increases, the bands in the intrinsic region
are pushed down in energy, narrowing the tun-
neling barrier and allowing tunneling current
Figure 1. Simulated Tunnel n-FETs. (a) Single-gate. (b) DG. SiO2 and high- κ to flow, as shown in Figure 2(b).
gate dielectrics were studied. tdielectric = 3 nm (physical) and Lintrinsic = 50 nm. Drain
doping (n+) = 5 °— 1018 atoms/cm3 and source doping (p+) = 1020 atoms/cm3. In order to be consistent with MOSFET technolo-
gy, the names of the device terminals are chosen
such that voltages are applied in a similar way
This paper explains the structure of a Tunnel FET and for Tunnel FET operation. Since a reverse bias is needed
how it functions (in Section II), and discusses subthresh- across the p-i-n structure in order to create tunneling
old slope for both MOSFETs and Tunnel FETs (in Section and since an NMOS operates when positive voltages are
III). Section IV shows how the novel DG design, with applied to the drain and gate, the n-region is referred to
an optimized silicon body thickness and a high-κ gate as the drain and the p+ region as the source.
dielectric, results in improved device characteristics in
terms of current and subthreshold swing, and discusses Doping has been optimized in order to create the maxi-
the 2-D nature of this device. The effects of temperature mum ON-current, while keeping OFF-current low. As
are also mentioned. discussed in the study in [8], it is desirable to have a
high source doping (around 1020 atoms/cm3 or even
higher) but a lower drain doping. For these simulations,
II. DEVICE OPERATION AND STRUCTURE the doping levels were 1 × 1020, 1 × 1017, and 5 × 1018
The investigated device structure is a lateral n-type atoms/cm3 for the source, intrinsic, and drain regions,
Tunnel FET in a thin silicon layer, isolated from the respectively.
substrate by a dielectric layer. The basic design is a
The work function chosen for the gate contact is 4.5 eV,
gated p-i-n diode. The tunneling takes place in this
corresponding to a metal gate stack. This could corre-
device between the intrinsic and p+ regions. Schemat-
spond to a stack comprised of tungsten (W) and titanium
ics of two of the devices simulated are shown in Figure
nitride (TiN) [16].
1; here, our discussions will primarily focus on the

Figure 2. Device structure corresponds to Fig. 1. (a) Schematic of energy-band diagram of the OFF-state of the Tunnel FET. Vd = 1
V and Vg = 0 V. In this state, the only current is p-i-n diode leakage current. (b) Schematic of energy-band diagram of the ON-state of
the Tunnel FET. In this state, the energy barrier is thin enough that electrons can tunnel from the valance band of the p+ region to the
conduction band of the intrinsic region. Vd = 1 V and Vg = 1.8 V.

January, February, March 2008 Page 5 The Simulation Standard

III. SUBTHRESHOLD SWING The benefits of a DG Tunnel FET over a DG MOSFET is
The subthreshold swing of a device is defined as the shown in Figure 3, which compares the Id–Vg character-
change in gate voltage which must be applied in order to istics of an optimized asymmetrical DG MOSFET from
create a one decade increase in the output current or [19] with those of a simulated DG Tunnel FET, being
proposed for the first time in this paper. The two de-
vices have the same dimensions for dielectric thickness
(3 nm), channel length (i-region length in the Tunnel
FET, equal to 50 nm), and body thickness (10 nm). The
The subthreshold swing of a MOSFET is limited by the dif- optimized DG Tunnel FET uses a high-κ gate dielectric
fusion current physics of the device in weak inversion, such with a dielectric constant of 29, as will be discussed
that the minimum possible swing in an ideal device is later. It is important to notice the difference between
the subthreshold regions in these two types of devices.
A MOSFET has a constant slope between the OFF-state
and threshold. A Tunnel FET, however, demonstrates a
which is about 60 mV/dec at room temperature (300 K). slope that is steeper (smaller swing) closer to the OFF-
state and less steep closer to threshold and varies as a
A Tunnel FET, on the other hand, does not experience the function of the gate voltage. Since the threshold volt-
same physical limitation, because the current mechanism age of a Tunnel FET cannot be extracted using certain
relies on the tunneling-barrier width rather than the for- standard MOSFET techniques, in this paper, we use the
mation of an inversion channel. Starting from Hurkx’s constant-current method, with a threshold current of
band-to-band tunneling model [17, eq. (12)], as used in 10 -7 A/µm.
Silvaco Atlas [18], the subthreshold slope for a Tunnel FET
can be expressed in terms of the gate voltage as It is clear that the swing for the Tunnel FET in Figure 3
is lower than that of the MOSFET, whether we look at
the point slope or the average slope. The point value of
S is defined as the minimum swing value at any point
on the Id–Vg curve. The average S value is calculated
where the constant is determined by device dimensions between the voltage at which the current begins to in-
and material parameters. Equation (3) shows that, in crease with increasing gate voltage, and the threshold
Tunnel FETs, the subthreshold slope is highly dependent voltage. These two values are different because S is a
on the gate voltage, and one should distinguish between function of Vg. Their extraction is shown in the inset of
the point and the average slopes (the latter being the Figure 3.
more important for switch performance). This is an im-
portant remark for future benchmarking of new abrupt A key issue in future DG Tunnel FETs is the simultane-
switch solutions, for which most reports currently point ous optimization of Ion/Ioff and subthreshold swing. A
to the optimization of the point slope only. basic analytical formulation of the tunneling probabil-
ity T(E), for ultrathin films and gate oxides, has been
derived in the study in [20] and shows that

where m* is the effective carrier mass, Eg is the bandgap,

ΔΦ is the energy range over which tunneling can take
place, and tox, tSi, εox, and εSi are the oxide and silicon film
thickness and dielectric constants, respectively. Equa-
tion (4) suggests that high-κ dielectrics would favor an
increased tunneling rate. This comes from the improved
electrical coupling between the gate and the tunneling
junction due to the increased gate capacitance. In con-
trast with a MOSFET, the current has an exponential
Figure 3. Comparison of simulated DG-Tunnel-FET character- dependence on the square root of the gate capacitance
istics with those of an optimized asymmetrical DG MOSFET rather than a linear one. Based on this observation, we
(from [13]). While the subthreshold slope is constant for a focus our device optimization on DG Tunnel FETs with
MOSFET in the subthreshold region, it is a function of Vg for high-κ gate dielectrics rather than on the engineering
a Tunnel FET. Both devices have L = 50 nm, tbody = 5 nm, and
of the material bandgap (as in previous approaches [10],
tdielectric = 3 nm. Vd = 1 V. Inset: Extraction of the average slope,
and the point at which the point slope is measured. [11] that proposed Tunnel FETs with SiGe).

The Simulation Standard Page 6 January, February, March 2008

IV. RESULTS AND DISCUSSION

A. Simulation Parameters
All simulations were done in Silvaco ATLAS, version
5.11.24.C, which uses a nonlocal Hurkx band-to-band
tunneling model [18]. This version of Atlas shows better
physical consistency over the version used in a previous
publication [21], which used a local band-to-band tun-
neling (BTB) model. The previously used local model
calculates a generation rate at each mesh node from the
magnitude of the electric field. In contrast, the currently
used nonlocal model works by calculating the tunnel-
ing probability from the energy-band diagrams across
the device. The simulations use a very fine mesh across
the region where the tunneling takes place, from which
energyband profiles and the energies for which band-
to-band tunneling is permitted, are determined. The
positions for the start and end of tunneling are found for
each energy and are used to calculate the current in that
energy range. ATLAS uses a two-band approximation
for the evanescent wavevector and a carefully applied
Wentzel–Kramer–Brillouin method.

Figure 5. (a)Width of energy barrier, for band-to-band tunnel-

ing, versus Vg, for different values of the gate-dielectric con-
stant. (b) Drain current versus energybarrier width for different
values of the gate-dielectric constant.

Gate leakage was neglected in these simulations and can

be expected to limit the OFF-current in fabricated Tunnel
FETs. Bandgap narrowing was enabled.

B. Double Gate (DG)

In an integrated DG-CMOS/DG-Tunnel-FET process,
the Tunnel FETs will benefit from the added gate, such
that the current will be at least doubled. In this way, the
ON-current is boosted, while the OFF-current, still in the
femtoamperes or picoamperes range, increases by the
same factor but remains extremely low. It is worth noting
that, for ultrathin silicon-on-insulator (SOI) MOSFETs,
some reports suggest that this improvement can be even
higher when volume inversion takes place [22].

C. High-κ Gate Dielectric

An even higher ON-current and decreased subthreshold
swing can be obtained by the careful choice of a gate dielec-
tric. As shown in Figure 4(a), current increases as the gate
dielectric constant increases. Here, Si3N4 and two high-κ
Figure 4. (a) DG-Tunnel-FET characteristics for various gate dielectrics, HfO2 and ZrO2, are compared to SiO2, all with
dielectrics. ε = 3.9 corresponds to SiO2, ε = 7.5 to Si3N4, ε = 21 a physical thickness of 3 nm. The high-κ materials have
to HfO2, and ε = 29 to ZrO2. Lintrinsic = 50 nm, tdielectric = 3
dielectric constants of 21 and 29, respectively. The reduced
nm, and t Si = 10 nm. Vd = 1 V. (b) Characteristics of a simplified
single-gate NMOSFET for various gate dielectrics. Junctions effective oxide thickness provided by these dielectrics offers
were ideally abrupt, as for the Tunnel FET, with source and a solution to the low-ON-current problem experienced by
drain doped to 1020 and the p-type body doped to 1017, L = 50 some existing Tunnel FETs at CMOS-compatible voltages.
nm, tdielectric = 3 nm, and t Si = 5 nm. Vd = 1 V. The OFF-current is less than 1 fA.

January, February, March 2008 Page 7 The Simulation Standard

Figure 6. DG Tunnel FET characteristics, normalized for each Figure 7. log(ID) versus 1/ε0.5ox ; the linearity of the plot is in
gate-dielectric constant (drain current/gate-dielectric con- good agreement with the proposed modeling in (4).
stant). Vd = 1 V. The increase in drain current is not linearly
proportional to the increase in gate capacitance as it would be
for MOSFET. Device corresponds to Fig. 1.

Interestingly, the ON-current does not increase merely constant of that device. From this figure, it is clear that
proportionally to the increase in the gate capacitance, the improvement in current cannot be simply attributed
as it would for a MOSFET. A simplified MOSFET 2-D to a proportional increase of the gate capacitance with
structure has been designed for numerical simulation the gate-dielectric constant.
in order to show the difference between the two [Figure
4(b)]. For Tunnel FETs, as we saw in (4), the improved In addition to improved Ion, both the point and average
coupling between the gate and the tunneling barrier subthreshold swing improve as the result of the better
has an exponential effect rather than a linear one. The gate coupling given by a high-κ dielectric. By raising
ON-current of a Tunnel FET depends on the width of the
the ON-portion of the Id–Vg curve [see Figure 4(a)], we
energy barrier between the intrinsic and p+ regions, and effectively “uncover” a steeper part of the curve in the
the current increases exponentially with a reduction in subthreshold, decreasing the point swing. The average
this barrier width. Figure 5(a) shows the dependence of swing is also much improved with a high-κ dielectric,
the energy-barrier width on the gate voltage for the gate- since the threshold voltage falls on a steeper part of the
dielectric constants studied. The barrier width was ex- curve. In contrast, the MOSFET swing hits the 60-mV/
tracted from the simulated band diagrams at a distance dec limit [Figure 4(b)] and cannot improve further.
of 2.5 nm from the dielectric surface, with 1 V applied to Figure 7 shows the linear relationship between log(ID)
the drain and the source grounded. Figure 5(b) shows and εox-0.5 , which supports what we expected to see from
the exponential dependence of the simulated tunneling (4). While high-κ dielectrics have advantages for device
current on the barrier width. Figure 6 shows the normal- characteristics, when put directly in contact with a silicon
ized Id–Vg characteristics for different gate dielectrics, channel, they can lead to defects at the semiconductor/
with each drain–current divided by the gate-dielectric dielectric interface. Although Tunnel FETs might be less

Figure 8. DG-Tunnel-FET characteristics for a structure with 2 Figure 9. DG-Tunnel-FET Id–Vg characteristics for various
nm of a high- κe dielectric (ε dielectric = 29) with a 1-nm inter- silicon body thicknesses. Lintrinsic = 50 nm, tdielectric = 3 nm, and ε
facial layer of oxynitride (ε dielectric = 5.7), dielectric
= 29. Vd = 1 V.

The Simulation Standard Page 8 January, February, March 2008

Figure 10. Ratio Ion /Ioff as a function of the silicon layer thick- Figure 11. (Left y axis) Point subthreshold swing and (right y
ness, for εdielectric = 29. A maximum, the optimum point, occurs in axis) average subthreshold swing as a function of silicon layer
the thickness range of 7–8 nm, depending on the value of Vdd thickness for different gatedielectric constants. Lintrinsic = 50 nm
used. 1 V was applied to the drain. and tdielectric = 3 nm.

sensitive to changes in channel mobility than MOSFETs, and/or the existence of an interfacial layer. Although the
as will be discussed below, standard CMOS fabrica- current simulations aim to stay within optimistic limits,
tion techniques require an interfacial layer between a reoptimization of the design will be needed once the
the high-κ dielectric and the silicon channel. A Tunnel parameters of fabricated materials are known.
FET with a more CMOS-compatible dielectric layer has
been simulated, and the resulting Id–Vg curve is shown in D. Thin-Film Structure
Figure 8. The simulated device had 1 nm of oxynitride at SOI and silicon-on-nothing fabrication technology are
the silicon surface and 2 nm of ZrO2. It is clear that even two fabrication methods currently used to create DG
with an interfacial layer, the subthreshold slope and ON- devices. Both of these techniques are commonly used on
current are very much improved over the device with an thin films, down to several nanometers thick. The thick-
SiO2 gate dielectric. ness of a Tunnel FET influences the shape of its Id–Vg
High-κ dielectrics bring additional challenges such as curve, as shown in Figure 9.
the limitations of soft and hard dielectric breakdown. Several trends can be seen in this figure. First, OFF-cur-
Depending on the characteristics of fabricated high-κ rent, which depends on the cross section of the p-i-n
dielectric layers, it may be necessary to limit applied gate structure, slightly decreases as expected with thickness.
voltages more than what is reported here. For example, As the film gets thinner than 10 nm, ON-current starts
depending on whether the structure of a HfO2 layer is to drop, possibly due to the reduced cross-sectional area
more tetragonal or cubic, the breakdown field could be 3.9 available for current flow. Due to these trends, the ratio
or 6.7 MV/cm, leading to a breakdown voltage of Vg = 1.17 Ion/Ioff will have a maximum when plotted against silicon-
V or 2.01 V [23]. Of course, these voltage numbers would layer thickness. Figure 10 shows that this optimum value
change depending on the high-κ dielectric thickness occurs when tSi is between 7 and 8 nm, depending on the

Figure 12. Dependence of the Tunnel FET subthreshold slope Figure 13. log(ID ) versus 1/t0.5Si at different gate voltages; the
on gate voltage for different dielectric constants, from numeri- relationship is approximately linear, in agreement with the pro-
cal simulation. Each curve goes up to the threshold voltage of posed modeling of (4).
that device. L = 50 nm, tdielectric = 3 nm, and tSi = 10 nm.

January, February, March 2008 Page 9 The Simulation Standard

 The relationship between the drain current and the body
thickness can be seen in (4): log(ID) is linearly dependent
on t-0.5Si . Figure 9 shows that this relation may hold true
for devices thicker than about 7 nm, but when the sili-
con body is too thin, the drain current is limited by the
reduced body thickness. Figure 13 shows the extraction
of the relationship between log(ID) and t-0.5Si for various
values of the gate voltage. This behavior will need to be
explored further.

Similar results are expected for a p-type device, which

has opposite doping from an n-type device [21].

E. Two-Dimensional Simulations
All simulations carried out in Silvaco ATLAS were 2-D,
and it is informative to look at vertical cross sections of
the energy bands of the Tunnel FET, as well as contour
plots in two dimensions, in order to understand the
functioning of the device. All diagrams are shown for
single-gate devices because, with the models currently
used, DG devices show identical results, symmetrical for
the two halves.

Looking first at the x direction component of the electric

field across a device which is ON [Figure 14(a)], we see
Figure 14. (a) Contour plot of the x-component of the electric field that the electric field is close to zero nearly everywhere.
in a singlegate Tunnel FET biased with Vd = 1 V and Vg = 1.8 V, in Between the intrinsic and p+ regions, where the tunnel-
overdrive, with tdielectric = 3 nm and εdielectric = 29. (b) Contour plot of the ing takes place, we see a high positive field throughout
potential of the same device under the same bias conditions. the depth of the device. In the potential contour plot for

value chosen for VDD, where Ion is taken at Vg = VDD. The

maximum ratio is about 2 × 1011, and as a comparison,
the optimized asymmetrical DG MOSFET from [19] has
an Ion/Ioff ratio of 106 with Ion taken at Vg = 1.5 V. The order
of magnitude of the Ion/Ioff ratio is not dramatically modi-
fied by a variation of the film thickness, which would be
advantageous if there were variations of body thickness
in devices on thin films.

Figure 9 also reveals that both the average and point val-
ues of subthreshold swing become lower as thickness de-
creases, as shown in Figure 11. The subthreshold swing also
decreases as high-κ dielectrics are used. While the point
swing is lower than the 60-mV/dec limit for MOSFETs
for all dielectrics and thicknesses simulated, the average
swing is lower than this limit only for a high-κ dielectric
with a constant of 29 (ZrO2) and a silicon body thickness
of less than 10 nm. The dependence of swing on the gate
voltage up to the threshold voltage is shown in Figure 12,
demonstrating that, at low gate voltages, Tunnel FETs have
a subthreshold swing under the 60-mV/dec MOSFET limit.

Clearly, these values of the average swing depend upon

our chosen definition for the threshold voltage. A lower
constant current value would lower the threshold voltage
Figure 15. Current flowlines for the same Tunnel FET as that shown
and, in turn, would advantageously lower the average
in Fig. 14, with (a) Vg = Vt (obtained using the constant-current tech-
swing values. It is worth mentioning, however, that quali- nique) and (b) Vg = 1.8 V.
tatively, all the trends of the curves remain the same.

The Simulation Standard Page 10 January, February, March 2008

 Inspection of some vertical energy-band cross sections
can help in understanding this current flow. Figure 16(a)
shows the energy bands taken vertically at the junction
between the source and intrinsic regions, where the
band-to-band tunneling takes place. The energy is lower
at the dielectric surface than deep in the body, particu-
larly at high Vg, as can also be noticed in the potential
contours where we see that the tunnel junction (the
abrupt change in potential) is more in the source near the
dielectric and more in the intrinsic region deeper in the
body. Therefore, just at this junction, electrons will want
to go toward the dielectric, to lower energy. Figure 16(b)
shows the energy bands cutting vertically through the
very center of the intrinsic region. Here, the bands are
nearly flat, and the electrons no longer stay as close to the
gate dielectric, as evidenced by the current flowlines.

The current-flow pattern promises to give an advantage

over conventional MOSFETs in terms of the effects of
surface roughness on device characteristics. Tunnel FETs
should be less affected by variations in mobility due to the
current being less confined to the surface under the gate.

F. Temperature
The temperature dependence of silicon Tunnel FETs
with an SiO2 gate dielectric has been reported in [9]
and [12]. Tunnel FETs with a high-κ dielectric show the
same general trends: the OFF-current, caused by the
generation of carriers in a reverse-biased junction, in-
creases with temperature, while the ON-current, coming
from band-to-band tunneling, changes only slightly, as
Figure 16. Cross sections of the energy bands of the same shown in Figure 17. The inset of Figure 17 shows that the
device as that shown in Figs. 14 and 15, taken vertically from subthreshold swing of the Tunnel FET for fixed values
the dielectric interface through the body. (a) Cross section at x
of Vg is nearly constant as temperature increases, unlike
= 150 nm, just at the junction between the intrinsic and p+ re-
gions, where tunneling takes place. (b) Cross section at x = 125 that of a MOSFET, which degrades proportionally to the
nm, at the center of the intrinsic region. increase in temperature, as can be seen in (2). Due to the
rising OFF-current, the average subthreshold swing of
Tunnel FETs will significantly degrade with increasing
this same device in the same state [Figure 14(b)], we see temperature, but beyond the leakage level, the current
that the potential drops abruptly at the tunnel junction, characteristics remain nearly unchanged.
and once again, this holds true for the entire device
depth, not just at the surface.

In the diagrams of current flowlines, shown at the

threshold voltage [Figure 15(a)] and in overdrive [Fig-
ure 15(b)], it is clear that the current does not stay close
to the gate dielectric as in a MOSFET. As the electrons
moves from right to left (source to drain) in the Tunnel
FET, they move parallel to the interface through most
of the source, then move away from the dielectric in-
terface at about the location of the tunnel junction and,
then, attracted by the positive voltage on the gate, flow
closer to the interface before spreading back out and
passing through the drain parallel to the interface, as Figure 17. Id–Vg characteristics for various temperatures. Vd = 1
they were in the source (electrical contacts are on the V. As temperature increases, Ioff increases, but Ion changes very
little. Inset: Slope at specific Vg values, versus temperature in
sides of the source and drain.)
Kelvin. We see that these values of slope are only slightly af-
fected by changes in temperature.

January, February, March 2008 Page 11 The Simulation Standard

The use of a high-κ dielectric rather than SiO2 leads [7] J. Appenzeller, Y.-M. Lin, J. Knoch, and P. Avouris, “Band-to-band
tunneling in carbon nanotube field-effect transistors,” Phys. Rev.
to a decrease in the threshold-voltage shift caused by Lett., vol. 93, no. 19, pp. 196805-1–196805- 4, Nov. 2004.
temperature. This is to be expected with the constant-
[8] P.-F. Wang, K. Hilsenbeck, T. Nirschl, M. Oswald, C. Stepper, M.
current method of Vt extraction, since with a higher Weis, D. Schmitt-Landsiedel, and W. Hansch, “Complementary
dielectric constant, Vt falls on a steeper part of the Id–Vg tunneling transistor for low power application,” Solid State Elec-
curve. While ΔV / T is in the range of 1–2 mV/K for Si/
Vt/Δ tron., vol. 48, no. 12, pp. 2281–2286, Dec. 2004.

SiO2 Tunnel FETs [12] and MOSFETs, we find that ΔVt/ΔT [9] K. Bhuwalka, M. Born, M. Schindler, M. Schmidt, T. Sulima, and
I. Eisele, “P-channel tunnel field-effect transistors down to sub-
is 0.2–0.3 mV/K for Tunnel FETs with a gate-dielectric
50 nm channel lengths,” Jpn. J. Appl. Phys., vol. 45, no. 4B, pp.
constant of 21. 3106–3109, Apr. 2006.

[10] K. Bhuwalka, J. Schulze, and I. Eisele, “Scaling the vertical tunnel

V. CONCLUSION FET with tunnel bandgap modulation and gate workfunction engi-
neering,” IEEE Trans. Electron Devices, vol. 52, no. 5, pp. 909–917,
We proposed and discussed the basic static opera- May 2005.
tion, and studied by simulation the characteristics of [11] K. Bhuwalka, J. Schulze, and I. Eisele, “Performance enhancement
a DG Tunnel FET as a better-than-60-mV/dec current of vertical tunnel field-effect transistor with SiGe in the delta p+
layer,” Jpn. J. Appl. Phys., vol. 43, no. 7A, pp. 4073–4078, 2004.
switch. The investigated Tunnel FET showed improved
characteristics including higher ON current and a [12] M. Born, K. Bhuwalka, M. Schindler, U. Abelein, M. Schmidt, T.
Sulima, and I. Eisele, “Tunnel FET: A CMOS device for high tem-
lower subthreshold swing, after the proposed design perature applications,” in Proc. 15th Int. Conf. Microelectron., 2006,
modifications: a double gate, a high-κ gate dielectric, pp. 124–127.
and an optimized silicon body thickness. The DG and [13] T. Nirschl, S. Henzler, J. Fischer,M. Fukle, A. Bargagli-Stoffi, M.
high-κ dielectric raise ON-current to 0.23 mA at Vg = Sterkel, J. Sedlmeir, C. Weber, R. Heinrich, U. Schaper, J. Einfeld,
1.8 V and provide a corresponding improvement in the R. Neubert, U. Feklmann, K. Stahrenberg, E. Ruderer, G. Geor-
gakos. R. Kakoschke, W. Hansch, and D. Schmitt-Landsiedel,
average subthreshold swing, as low as 57 mV/dec, and “Scaling properties of the tunneling field effect transistor (TFET):
a minimum point swing of 11 mV/dec. An optimum Device and circuit,” Solid State Electron., vol. 50, no. 1, pp. 44–51,
silicon body layer thickness of between 7 and 8 nm was Jan. 2006.

found for the studied device with a gate length of 50 [14] Q. Zhang, W. Zhao, and A. Seabaugh, “Analytic expression and
approach for low subthreshold-swing tunnel transistors,” in Proc.
nm, maximizing the ratio Ion/Ioff to 2 × 1011. In addition,
DRC, Santa Barbara, CA, Jun. 20–22, 2005, pp. 161–162.
the subthreshold swing for fixed values of Vg remains
[15] Semiconductor Industry Association (SIA), International Technology
nearly unchanged as temperature increases. The Tunnel Roadmap for Semiconductors (ITRS), 2005. [Online]. Available:
FET’s promising behavior makes it a strong candidate to http:// www.itrs.net/
complement or replace MOSFET technology, particularly [16] B. Guillaumot, X. Garros, F. Lime, K. Oshima, B. Tavel, J. A. Chrob-
for LSTP applications. oczek, P. Masson, R. Truche, A. M. Papon, F. Martin, J. F. Dam-
lencourt, S. Maitrejean,M. Rivoire, C. Leroux, S. Cristoloveanu, G.
Ghibaudo, J. L. Autran, T. Skotnicki, and S. Deleonibus, “75 nm
ACKNOWLEDGMENT damascene metal gate and high-k integration for advanced CMOS
devices,” in IEDM Tech. Dig., Dec. 8–10, 2002, pp. 355–358.
The authors would like to thank K. Bhuwalka for some
[17] G. Hurkx, D. Klaassen, and M. Knuvers, “A new recombination
enlightening discussions and A. Ferron at Silvaco for the model for device simulation including tunneling,” IEEE Trans. Elec-
continuing support with ATLAS simulations. tron Devices, vol. 39, no. 2, pp. 331–338, Feb. 1992.

[18] ATLAS User’s Manual

Manual, Silvaco Int., Santa Clara, CA, May 26, 2006.
[19] K. Kim and J. Fossum, “Double-gate CMOS: Symmetrical- versus
asymmetrical-gate devices,” IEEE Trans. Electron Devices, vol. 48,
REFERENCES no. 2, pp. 294–299, Feb. 2001.
[1] J. Quinn, G. Kawamoto, and B. McCombe, “Subband spectroscopy by
[20] J. Knoch and J. Appenzeller, “A novel concept for field-effect tran-
surface channel tunneling,” Surf. Sci
Sci., vol. 73, pp. 190–196, May 1978.
sistors—The tunneling carbon nanotube FET,” in Proc. 63rd DRC,
[2] T. Baba, “Proposal for surface tunnel transistors,” Jpn. J. Appl. Jun. 20–22, 2005, vol. 1, pp. 153–156.
Phys., vol. 31, no. 4B, pp. L455–L457, Apr. 1992.
[21] K. Boucart and A. M. Ionescu, “Double gate tunnel FET with ultra-
[3] W. Reddick and G. Amaratunga, “Silicon surface tunnel transistor,” thin silicon body and high- k gate dielectric,” in Proc. ESSDERC,
Appl. Phys. Lett., vol. 67, no. 4, pp. 494–496, Jul. 1995. 2006, pp. 383–386.

[4] J. Koga and A. Toriumi, “Three-terminal silicon surface junction [22] F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa,
tunneling device for room temperature operation,” IEEE Electron “Double-gate silicon-on-insulator transistor with volume inversion:
Device Lett., vol. 20, no. 10, pp. 529–531, Oct. 1999. A new device with greatly enhanced performance,” IEEE Electron
Device Lett., vol. EDL-8, no. 9, pp. 410–412, Sep. 1987.
[5] W. Hansch, C. Fink, J. Schulze, and I. Eisele, “A vertical MOS-
gated Esaki tunneling transistor in silicon,” Thin Solid Films, vol. [23] J. McPherson, J.-Y. Kim, A. Shanware, and H. Mogul, “Thermo-
369, no. 1/2, pp. 387–389, Jul. 2000. chemical description of dielectric breakdown in high dielectric con-
stant materials,” Appl. Phys. Lett., vol. 82, no. 13, pp. 2121–2123,
[6] C. Aydin, A. Zaslavsky, S. Luryi, S. Cristoloveanu, D. Mariolle, D. Mar. 2003.
Fraboulet, and S. Deleonibus, “Lateral interband tunneling transis-
tor in silicon-on-insulator,” Appl. Phys. Lett., vol. 84, no. 10, pp.
1780–1782, Mar. 2004.

The Simulation Standard Page 12 January, February, March 2008