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Innovus block - Copy - Copy 1

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225 views22 pages

Innovus block - Copy - Copy 1

Uploaded by

RA NDY

Copyright:

© All Rights Reserved
Download as PPTX, PDF, TXT or read online from Scribd
Download as pptx, pdf, or txt
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90nm project implementation on Innovus tool Prepared By : Subbarao.

V
Design details
Initialize the design
Sanity checks
Project Floorplanning
outline : Powerplanning
Placement
Clock tree synthesis
Routing
Design details :

Technology 90nm
STD cells count 26584
Macro count 7
Ports count 301
Metal layers 9
clocks 4
Frequency/Time period 1MHZ/1ns
Initialize the design :
After importing the design with read_design then we see all the macros
and standard cells are placed at the left bottom corner of the block.

PD
Module Macro
s s

STD.Cel
Sanity
checks :
• Checked the quality of
netlist and constraints
before going to floorplan.
• Check_design
• Check_timing
• Check_library
Floorplanning :
Created a new rectilinear shape floorplan by manually cutted the floorplan
shape using floorplan editor options in the tool.

 Creating new floorplan by using cmd :


I/P-Ports
Create_floorplan - box_size core and die coordinates values.
 Placed the macros as per guidelines.
 Placed the input and output pins by using pin editor
opring from the tool and make it place in different
locations by using the belowe cmd.
O/P-  Command used : edit_pin -start { x y co-ordinates} - end
Ports { x y co-ordinates} -pin [get_obj_name [get_ports
[all_inputs]]] - include_rectilinear_edge - spacing 20 - layer
M3 -spread_type range.
All macros should be placed and fixed

Ports should be fixed

Check place
Floorplan
checks : Check pin assignment

CheckFplan [ it will check the regions placement &


power domains placement]

Physical cells missing's (proper row cutting) otherwise


poly, ody, latch-up issues will come like base drc's come
Utilization report : report_density_map & check_pin_assignment
Powerplanning

In powerplanning stage the PG network is created and distribute the power to


each cell in design like std.cells, macrso and ports.
In powerplan, see the
power stripes all are exist
or not.
Verify_pg_connectivity.
Powerplan
checks :
Check_drc

Check_missing_vias
Powerplan checks
:
Placement :
Placing the std.cells and checked the congestions, Drv's & timing and all
are under control.
Blockages:
Blockages are applied manually in experimental block parallelly for
making a congested block.
Timing report : Setup & Hold
Report_timing - early Report_timing - late
Clock tree synthesis : report_clock_timing –type skew
Clock tree was building for distributing the clock to all sequential pins and
checked skew and latencies.
Clock tree synthesis :
report_clock_timing – type latency
Timing : report_timing –type early
Timing : report_timing –type late
Clock tree synthesis :
In cts stage the inverters-19 and clk buffers-16 are extra-added cells in the design.
Routing :
Routing is the process of creating physical connection based on the logical
connectivity. The signal pins are connected by metal interconnects. The routed
metal path must meet the timing, Drv's, skew and drc's should be under control.

Metal Routing's Routed db


DRC's :

The Matel spacing violations are fixed by given some space between metals manually so
that the violation fixed.

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