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    Chapter 5 IMP Question

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    nirav34
    This document contains 4 questions and answers about combinational logic circuits. 1) A full adder circuit is implemented using a decoder, with 3 inputs (X, Y, Z) and 2 outputs (Sum, Carry). 2) A 5-to-32 line decoder is constructed using 4 3-to-8 line decoders with enables and a 2-to-4 line decoder. 3) A circuit is designed to calculate the square of a 3-bit number using a ROM. The ROM has 3 address inputs and 4 data outputs. 4) A full adder is implemented using two 4x1 multiplexers, with X, Y as select lines and Cin as

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    Chapter 5 IMP Question

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    This document contains 4 questions and answers about combinational logic circuits. 1) A full adder circuit is implemented using a decoder, with 3 inputs (X, Y, Z) and 2 outputs (Sum, Carry). 2) A 5-to-32 line decoder is constructed using 4 3-to-8 line decoders with enables and a 2-to-4 line decoder. 3) A circuit is designed to calculate the square of a 3-bit number using a ROM. The ROM has 3 address inputs and 4 data outputs. 4) A full adder is implemented using two 4x1 multiplexers, with X, Y as select lines and Cin as

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    This document contains 4 questions and answers about combinational logic circuits. 1) A full adder circuit is implemented using a decoder, with 3 inputs (X, Y, Z) and 2 outputs (Sum, Carry). 2) A 5-to-32 line decoder is constructed using 4 3-to-8 line decoders with enables and a 2-to-4 line decoder. 3) A circuit is designed to calculate the square of a 3-bit number using a ROM. The ROM has 3 address inputs and 4 data outputs. 4) A full adder is implemented using two 4x1 multiplexers, with X, Y as select lines and Cin as

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    168 views6 pages

    Chapter 5 IMP Question

    Uploaded by

    nirav34
    This document contains 4 questions and answers about combinational logic circuits. 1) A full adder circuit is implemented using a decoder, with 3 inputs (X, Y, Z) and 2 outputs (Sum, Carry). 2) A 5-to-32 line decoder is constructed using 4 3-to-8 line decoders with enables and a 2-to-4 line decoder. 3) A circuit is designed to calculate the square of a 3-bit number using a ROM. The ROM has 3 address inputs and 4 data outputs. 4) A full adder is implemented using two 4x1 multiplexers, with X, Y as select lines and Cin as

    Copyright:

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    of 6

    CHAPTER-5 COMBINATIONAL LOGIC WITH MSI AND LSI(IMP QUE.

    Que 1--Combinational logic implementation-Full adder with a decoder Ans- A Full Adder is a combinational circuit that performs the arithmetic sum of three input bits. It consists of three inputs and two outputs. Three of the input variables can be defined as X,Y,Z and the two output variables can be defined as Sum, Carry. Truth Table:

    X 0 0 0 0 1 1 1 1 So,

    INPUTS Y 0 0 1 1 0 0 1 1 S(X,Y,Z)=(1,2,4,7) C(X,Y,Z)=(3,5,6,7)

    OUTPUTS Z 0 1 0 1 0 1 0 1 C 0 0 0 1 0 1 1 1 Sum 0 1 1 0 1 0 0 1

    Implementation of full-adder with a decoder:

    PREPARED BY ASST. PROF NIRAV PATEL

    Page 1

    Que 2- Construct a 5-to-32-line decoder with four 3-to-8-line decoders with enable and a 2to-4-line decoder. Use block diagrams for the components Ans-5-to-32-line decoder

    We need four 3- to -8 decoder for the last stage and one 2-to-4 decoder for selecting each of them at the first stage.

    PREPARED BY ASST. PROF NIRAV PATEL

    Page 2

    Que 3- Design a combinational circuit using a ROM. The circuit accepts a 3 bit number and generates an output binary number equal to the square of the input number. Ans-The first step is to derive the truth table for the combinational circuit. So for this example the truth-table is:

    PREPARED BY ASST. PROF NIRAV PATEL

    Page 3

    Three inputs and six outputs are needed to accommodate all possible numbers. We note that output B0 is always equal to input A0.So there is no need to generate B0 with a ROM since it is equal to an input variable. Moreover, output B1 is always 0, so the output is always known. We actually need to generate only four outputs with the ROM. So the minimum size ROM needed must have three inputs and four outputs. Three inputs specify eight words, so the ROM size must be 84.The ROM implementation is shown in the figure.

    PREPARED BY ASST. PROF NIRAV PATEL

    Page 4

    Que 4-Implement full-adder with two 41multiplexer. Ans-The truth table for the full adder is:

    X 0 0 0 0 1 1 1 1 Now for Multiplexer X,Y=Selection lines Bin=input For Sum

    INPUTS Y 0 0 1 1 0 0 1 1

    Cin 0 1 0 1 0 1 0 1

    OUTPUTS Cout Sum 0 0 0 1 0 1 1 0 0 1 1 0 1 0 1 1

    For Cout

    PREPARED BY ASST. PROF NIRAV PATEL

    Page 5

    Implement full adder with the help of two 41 multiplexer:

    PREPARED BY ASST. PROF NIRAV PATEL

    Page 6

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