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    Memory Interfacing With Example

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    Sachin Jaysenan
    The document discusses memory interfacing with the 8085 microprocessor. It provides examples of designing memory systems using techniques like absolute decoding and partial decoding. It also includes memory maps and interfacing diagrams for examples using EPROM and RAM ICs.

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    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd

    Memory Interfacing With Example

    Uploaded by

    Sachin Jaysenan
    7K views6 pages
    The document discusses memory interfacing with the 8085 microprocessor. It provides examples of designing memory systems using techniques like absolute decoding and partial decoding. It also includes memory maps and interfacing diagrams for examples using EPROM and RAM ICs.

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    8085

    Original Title

    7. Memory Interfacing With Example.pptx

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    The document discusses memory interfacing with the 8085 microprocessor. It provides examples of designing memory systems using techniques like absolute decoding and partial decoding. It also includes memory maps and interfacing diagrams for examples using EPROM and RAM ICs.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    7K views6 pages

    Memory Interfacing With Example

    Uploaded by

    Sachin Jaysenan
    The document discusses memory interfacing with the 8085 microprocessor. It provides examples of designing memory systems using techniques like absolute decoding and partial decoding. It also includes memory maps and interfacing diagrams for examples using EPROM and RAM ICs.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 6

    7.

    Memory Interfacing with Example

    19 Aug. 2013

    Module 1

    Memory interfacing
    Memory structure and its requirements. Basic concepts in memory interfacing. Address decoding and memory address.

    Basics of 8085:
    Types of memory and memory interfacing. Decoding techniques Absolute and Partial

    Prepared By AJIT SARAF

    Memory structure and its requirements (RAM)


    Input data Input buffer A10
    I N T E R N A L D E C O D E R

    Memory structure and its requirements (ROM)

    WR CS

    A11
    I N T E R N A L D E C O D E R

    A0

    R/W Memory N M 2048 8

    N = number of register M = word length A0

    EPROM 4096 8

    N = number of register M = word length

    Output buffer
    RD

    Output buffer Output data

    CS RD

    Output data Logic Diagram for RAM

    Logic Diagram for EPROM

    Prepared by AJIT SARAF

    7. Memory Interfacing with Example

    19 Aug. 2013

    Example: If a memory is having 13 address lines and 8 data lines, then the number of registers / memory locations = 2^13 = 8129 word length = 8 bit Note: The number of address lines of a microprocessor depends on the Size of the memory. No. of lines
    Memory size in bytes

    Basic concepts in memory interfacing (Rules)


    1) 8085 can access 64 KB of memory, since address bus is 16-bit. But it is not always necessary to use full 64Kbytes address space. The total memory size depends upon the application. 2) Generally EPROM is used as a program memory and RAM is used as data memory. when both are used then total 64 KB address will be shared by both. 3) The capacity of program memory and data memory depends on the application.

    1 2 3 4 5 6 7

    2 4 8 16 32 64 128

    8 9 10 11 12 13 14 15 16

    256 Bytes 512 Bytes 1024=1k 2048=2k 4096=4k 8129=8k 16384=16k 32768=32k 65536=64k

    Basic concepts in memory interfacing (Rules)


    4) It is not always necessary to select 1 EPROM and 1 RAM. We can have multiple EPROMs and multiple RAMs as per the requirement of application. 5) We can place EPROM / RAM anywhere in full 64 Kbytes address space. But program memory (EPROM) should be located from address 0000H since reset address of 8085 microprocessor is 0000H. 6) It is not always necessary to locate EPROM and RAM in consecutive memory addresses.

    Q.1) Design a microprocessor system for 8085 such that it should contain 8k byte of EPROM and 8k byte of RAM using 1) Absolute / Full Decoding 2) Partial / Linear Decoding. Solution:
    MEMORY ICs
    Starting address Of EPROM End address Of EPROM Starting address Of RAM End address Of RAM A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address

    0 0 0 0 0 0 0 0 0 0 1 1 1

    0 0 0 0

    0 0

    0 0 0 1 1 0 1

    0000H 1FFFH 2000H 3FFFH

    1 1 1

    1 1 1

    1 1

    0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1

    Prepared by AJIT SARAF

    7. Memory Interfacing with Example

    19 Aug. 2013

    1 uF X1

    D0-D7 VCC A0-A7 A8-A15 IOR IOW MEMR MEMW

    6 MHz X2 1 uF + 5V + 5V

    8085

    ALE LE

    WR A0 A7 RD IO/M

    G A 7 Y5

    READY

    AD0 AD7

    75 K RESETIN SW 1 uF

    7 4 3 7 3
    D0 D7

    4 B L Y6 S 1 Y1 C 3 Y2 8

    G1 G2

    D7- D0 A12 A11 A10 A9 A8 A7-A0 OE VCC

    D7- D0 A12 A11 A10 A9 A8 A7-A0 OE WR

    EPROM (8K) 2764


    G

    RAM (8K) 6264 CS

    TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA RESETOUT

    A8 A15

    A 7 4 A14 L Y0 B S 1 A15 C 3 Y1 8 G1 G2

    A13

    CS

    Absolute Decoding Technique / Full Decoding

    D0-D7 A0-A7 VCC A8-A15 IOR IOW MEMR MEMW

    Q.2) Design a microprocessor system for 8085 such that it should contain 16k byte of EPROM and 4k byte of RAM using 8 Kbyte EPROMs and 2k byte RAMs. Solution:
    Memory Ics
    s.a of EPROM1 e.a of EPROM1 s.a of EPROM2
    A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
    ADDRESS

    WR RD IO/M

    G A 7 Y5

    4 B L Y6 S Y1 1 C 3 Y2 8

    0 0 0 0 0 0 0 0

    0 0 0 0 1 1 1 1

    0 0 1 1 0 0 1 1

    0 1 0 1 X X X X

    0 1 0 1 X X X X

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0000H 1FFFH 2000H 3FFFH 4000H 47FFH 6000H 67FFH

    G1 G2

    D7- D0 A12 A11 A10 A9 A8 A7-A0 OE

    D7- D0 A12 A11 A10 A9 A8 A7-A0 OE WR

    e.a of EPROM2 s.a of RAM1 e.a of RAM1 s.a of RAM2

    EPROM (8K) 2764 CS

    RAM (8K) 6264 CS

    A13

    s.a of RAM2

    Linear Decoding Technique / Partial Decoding

    Prepared by AJIT SARAF

    7. Memory Interfacing with Example

    19 Aug. 2013

    D0-D7 VCC A0-A7 A8-A15 IOR IOW MEMR MEMW

    WR

    A 7 Y5 4 RD L Y6 B S 1 Y1 IO/M 3 C 8 Y2 G1 G2

    Q.3) Interface 2kb EPROM to 8085 using EPROM (1k X 4) chips, 74LS138 decoder and full address decoding and give the address map. Solution:
    Memory Ics
    s.a of EPROM1 e.a of EPROM1
    A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
    ADDRESS

    0 0 0 0 0 0 0 0

    0 0 0 0 0 0 0 0

    0 0 0 0 1 1 1 1

    0 0 0 0 0 0 0 0

    0 0 0 0 0 0 0 0

    0 0 0 0 0 0 0 0

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0000H 03FFH 0000H 03FFH 2000H 23FFH 2000H 23FFH

    VCC

    D7- D0 A12 A11 A10 A9 A8 A7-A0 OE D7- D0 A12 A11 A10 A9 A8 A7-A0 OE

    D7- D0 A10

    A9

    A8

    A7-A0 OE WR

    D7- D0 A10 A9

    A8

    A7-A0

    OE WR

    s.a of EPROM2 e.a of EPROM2 s.a of EPROM3 e.a of EPROM3

    EPROM (8K) 2764 CS

    EPROM (8K) 2764 CS

    RAM (2K) 6116 CS

    RAM (2K) 6116 CS

    A13
    A14

    G
    A 7 Y0 4 L Y1 S 1 Y2 3 8 Y3

    A11 A12

    A15

    s.a of EPROM4 e.a of EPROM4

    G1 G2

    A11 A12

    VCC

    D0-D7 A0-A7 A8-A15

    WR

    A 7 Y5 4 RD L Y6 B S 1 Y1 IO/M 3 C 8 Y2 G1 G2

    IOR IOW MEMR MEMW

    Q.4) Design an 8085 based system for the following specifications: (a) CPU working at 3 MHz. (b) 8kB EPROM using 4kB devices. (c) 4kB RAM using 2kB devices. (d) One 8259 PIC in I/O mapped I/O. (e) One 8255 in I/O mapped I/O. Draw the complete interfacing diagram with latches, chip select logic, Reset circuit.

    VCC

    D7- D4 A9

    A8 A7-A0 OE WR D3- D0 A9

    A8 A7-A0 OE WR

    D7- D4 A9 A8 A7-A0 OE WR D3- D0 A9 A8 A7-A0 OE WR

    EPROM (1K) CS

    EPROM (1K) CS

    EPROM (1K) CS

    EPROM (1K) CS

    A13

    A 7 Y0 4 A14 L B S 1 A15 3 Y1 C 8 G1 G2

    A12

    A11 A10

    Prepared by AJIT SARAF

    7. Memory Interfacing with Example

    19 Aug. 2013

    Solution: Memory Map:


    Memory Ics
    S.A. of EPROM1 E.A. of EPROM1 S.A. of EPROM2 E.A. of EPROM2 S.A. of RAM1 E.A. of RAM1 S.A. of RAM1 E.A. of RAM1
    A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ADDRESS

    I/O Map
    Ports and Registers Port A Port B Port C CWR 8259 Chip
    A7 A15 A6 A14 A5 A13 A4 A12 A3 A11 A2 A10 A1 A9 A0 A8 ADDRESS

    0 0 0 0 0

    1 1 1 1 1

    0 0 0 0 0

    0 0 0 0 1

    0 0 0 0 0

    0 0 0 0 0

    0 0 1 1 0

    0 1 0 1 0/1

    40H 41H 42H 43H 50/51H

    0 0 0 0 0 0 0 0

    0 0 0 0 0 0 0 0

    0 0 0 0 1 1 1 1

    0 0 1 1 0 0 1 1

    0 1 0 1 X X X X

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0 1 0 1 0 1 0 1

    0000H 0FFFH 1000H 1FFFH 2000H 27FFH 3000H 37FFH

    1 uF X1 WR 6 MHz X2 1 uF + 5V READY

    VCC

    D0-D7 A0-A7
    A8-A15 IOR IOW MEMR MEMW

    8085

    ALE LE

    A0 A7
    + 5V

    AD0 AD7

    75 K RESETIN SW 1 uF

    7 4 3 7 3
    D0 D7

    A 7 Y5 4 RD L Y6 B S 1 Y1 IO/M 3 C 8 Y2 G1 G2

    VCC

    D7- D0 A11 A10 A9

    A8 A7-A0 OE D7- D0 A11 A10 A9

    A8 A7-A0 OE

    D7- D0 A10

    A9

    A8

    A7-A0 OE WR

    D7- D0 A10 A9

    A8

    A7-A0

    OE WR

    EPROM 1(4K) CS

    EPROM2 (4K) CS

    RAM1 (2K) CS

    RAM2 (2K) CS

    TRAP RST 7.5 RST 6.5 RST 5.5 INTR INTA RESETOUT

    A 7 Y0 4 A13 L Y1 B S 1 Y2 A14 3 C 8 Y3 G1 G2

    A12

    A11 A11

    A8 A15

    A15

    Prepared by AJIT SARAF

    7. Memory Interfacing with Example

    19 Aug. 2013

    VCC

    D0-D7 A0-A7
    A8-A15 IOR IOW MEMR MEMW

    WR RD

    University Questions (ELECTRONICS)


    May-2012
    1) Design a system based on 8085 with following configuration (i) 8K x 8 EPROM using 4K x 8 chips (10 Marks) (ii) 8K x 8 RAM using 4K x 8 chips Draw memory map and interface diagram.

    A 7 Y5 4 L Y6 B S 1 Y1 IO/M 3 C 8 Y2 G1 G2

    + 5V

    Dec-2012
    VCC Vcc A0,A1 D0-D7 A0 D0-D7 SP/EN

    IR0

    A 7 Y4 4 A13 L B S 1 A14 3 C 8 Y5 G1 G2

    A12

    OE

    PA PB PC
    INTR INTA

    8 WR 2 5 5
    RESET OUT Reset

    OE

    8 WR 2 5 9
    INT INTA CS

    IR7
    CAS0 CAS1 CAS2

    CS

    A15

    2) Design 8085 based system with following specifications : (i) CPU operating at 3 MHz. (12 Marks) (ii) 16 KB program memory using 4 KB devices. (iii) 4 KB data memory using 2 KB devices. (iv) One 8 bit input port and one 8 bit output port performing interrupt driven I/O and interfaced in I/O mapped I/O mode. Use exhaustive decoding approach. Give detailed I/O map and memory map and neat interfacing diagram.

    Prepared by AJIT SARAF

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