Snx5Hvd251 Industrial Can Bus Transceiver: 1 Features 3 Description
Snx5Hvd251 Industrial Can Bus Transceiver: 1 Features 3 Description
Snx5Hvd251 Industrial Can Bus Transceiver: 1 Features 3 Description
SN55HVD251, SN65HVD251
SLLS545G – NOVEMBER 2002 – REVISED OCTOBER 2015
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN55HVD251, SN65HVD251
SLLS545G – NOVEMBER 2002 – REVISED OCTOBER 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 8 Detailed Description ............................................ 17
2 Applications ........................................................... 1 8.1 Overview ................................................................. 17
3 Description ............................................................. 1 8.2 Functional Block Diagram ....................................... 17
4 Revision History..................................................... 2 8.3 Feature Description................................................. 17
8.4 Device Functional Modes........................................ 19
5 Pin Configuration and Functions ......................... 4
6 Specifications......................................................... 4 9 Application and Implementation ........................ 21
9.1 Application Information............................................ 21
6.1 Absolute Maximum Ratings ...................................... 4
9.2 Typical Application .................................................. 24
6.2 ESD Ratings.............................................................. 4
9.3 System Example ..................................................... 26
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information .................................................. 5 10 Power Supply Recommendations ..................... 28
6.5 Supply Current .......................................................... 5 11 Layout................................................................... 28
6.6 Electrical Characteristics: Driver ............................... 5 11.1 Layout Guidelines ................................................. 28
6.7 Electrical Characteristics: Receiver .......................... 6 11.2 Layout Example .................................................... 29
6.8 VREF-Pin Characteristics ........................................ 6 12 Device and Documentation Support ................. 30
6.9 Power Dissipation Characteristics ............................ 7 12.1 Related Links ........................................................ 30
6.10 Switching Characteristics: Driver ............................ 7 12.2 Community Resources.......................................... 30
6.11 Switching Characteristics: Device ........................... 7 12.3 Trademarks ........................................................... 30
6.12 Switching Characteristics: Receiver........................ 8 12.4 Electrostatic Discharge Caution ............................ 30
6.13 Dissipation Ratings ................................................. 8 12.5 Glossary ................................................................ 30
6.14 Typical Characteristics ............................................ 9 13 Mechanical, Packaging, and Orderable
7 Parameter Measurement Information ................ 11 Information ........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
• Changed the value of HBM "All pins" From: ±14000 V To: ±6000 V. Changed the value of "CANH, CANL and GND"
From: ±6000 V To: ±14000 V in the ESD Ratings ................................................................................................................. 4
• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
• Changed the location of section "6.12 VREF-Pin Characteristics" to section 6.8 ................................................................. 6
D Package
8-Pin SOIC
Top View
D 1 8 RS
GND 2 7 CANH
VCC 3 6 CANL
R 4 5 Vref
Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
CANH 7 I/O High-level CAN bus line
CANL 6 I/O Low-level CAN bus line
CAN transmit data input (LOW for dominant and HIGH for recessive bus states), also called
D 1 I
TXD, driver input
GND 2 GND Ground connection
CAN receive data output (LOW for dominant and HIGH for recessive bus states), also called
R 4 O
RXD, receiver output
Mode select pin: strong pulldown to GND = high-speed mode, strong pull up to VCC = low-
RS 8 I
power mode, 10-kΩ to 100-kΩ pulldown to GND = slope control mode
VCC 3 Supply Transceiver 5-V supply voltage
VREF 5 O Reference output voltage
6 Specifications
6.1 Absolute Maximum Ratings (1) (2)
MIN MAX UNIT
Supply voltage, VCC –0.3 7 V
Voltage at any bus pin(CANH or CANL) –36 36 V
Transient voltage per ISO 7637, pulse 1, 2, 3a, 3b CANH, CANL –200 200 V
Input voltage, VI (D, Rs, or R) –0.3 VCC + 0.5 V
Receiver output current, IO –10 10 mA mA
Electrical fast IEC 61000-4-4, Classification CANH, CANL –3 3 kV
transient/burst B
Continuous total power dissipation (see Dissipation Ratings)
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground pin.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(1) All typical values are at 25°C and with a 5-V supply.
(1) All typical values are at 25°C and with a 5-V supply.
Copyright © 2002–2015, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: SN55HVD251 SN65HVD251
SN55HVD251, SN65HVD251
SLLS545G – NOVEMBER 2002 – REVISED OCTOBER 2015 www.ti.com
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(2) In accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
(3) In accordance with the High-K thermal metric definitions of EIA/JESD51-7.
150
74 RS = 0 V RS = 0 V
145
VCC = 5.5 V
tLOOP1 – Loop Time – ns
72
135
68
130
66
VCC = 4.5 V
VCC = 5.5 V
64 125
62 120
–40 –25 –10 5 20 35 50 65 80 95 110 125 –40 –25 –10 5 20 35 50 65 80 95 110 125
Figure 1. Recessive-to-Dominant Loop Delay vs Free-Air Figure 2. Dominant-to-Recessive Loop Delay vs Free-Air
Temperature Temperature
33 5
VCC = 5 V,
4.5
32 TA = 25°C,
RS = 0 V, 4
31 RL = 60 W, CANH
3.5
CL = 50 pF
30 3 VCC = 5 V,
TA = 25°C,
29 2.5 RS = 0 V,
2 D at 0V
28
1.5
27 CANL
1
26 0.5
25 0
0 250 500 750 1000 1250 1500 1750 2000 0 10 20 30 40 50 60 70 80
Figure 3. Supply Current (RMS) vs Signaling Rate Figure 4. Driver Output Voltage vs Output Current
4.5
VOD(D) – Dominant Differential Output Voltage – V
3
VOD - Driver Differential Output Voltage - V
VCC = 5 V,
4 TA = 25°C, VCC = 5.5 V
RS = 0 V, 2.5
3.5
D at 0V
3
2
VCC = 4.5 V
2.5 VCC = 5 V
1.5
2
1.5 1
1 RS = 0 V,
0.5 D at 0V,
0.5 RL = 60 W
0 0
0 10 20 30 40 50 60 70 80 –55 –40 0 25 70 85 125
TA – Free-Air Temperature – °C
IO - Driver Output Current - mA
Figure 6. Dominant Differential Output Voltage vs free-Air
Figure 5. Driver Differential Output Voltage vs Output
Temperature
Current
400
20
300
200
10
100
0 0
1 2 3 4 5 6 0 10 20 30 40 50 60 70 80 90 100
VCC – Supply Voltage – V RS - Slope Resistance - kW
Figure 7. Driver Output Current vs Supply Voltage Figure 8. Differential Output Transition Time vs Slope
Resistance (Rs)
0
−1
−1.50
VCC = 5 V
−2
VCC = 4.5 V
−2.50
−3
−50 0 50 100 150
TA − Free-Air Temperature −°C
Figure 9. Input Resistance Matching vs Free-Air Temperature
D VO(CANH)
II VOD
60 1%
VO(CANH) + VO(CANL)
2
Rs IIRs VOC
VI + IO(CANL)
VI(Rs) VO(CANL)
_
Dominant VO(CANH)
3.5 V
Recessive
2.5 V
1.5 V VO(CANL)
RNODE
CANH
D 60 W ± 1%
VI VOD
+
_ –7 V ≤ VTEST ≤ 12 V
RS
CANL
RNODE
CANH
D RL = CL =
VO
60 W ±1% 50 pF ±20%
VI (see Note B)
Rs +
(see Note A) VI(Rs) CANL
_
VCC
VI VCC/2 VCC/2
0V
tPLH tPHL
VO(D)
0.9V 90%
VO 0.5V
10% VO(R)
tr tf
CANH
VI(CANH) R IO
VID
VI(CANH) + VI(CANL)
VIC =
2
VO
VI(CANL) CANL
CANH
R
IO
VI
CANL CL = 15 pF
(see Note A) 1.5 V 20% (see Note B) VO
3.5 V
VI 2V 2.4 V
1.5 V
tPLH tPHL
VOH
VO 0.7 VCC 90% 0.3 VCC
10% 10%
VOL
tr tf
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤
6ns, tf ≤ 6ns, ZO = 50 Ω.
B. CL includes instrumentation and fixture capacitance within ±20%.
CANH
R
CANL
100 W
Pulse Generator
D at 0 V
15 µs Duration
or VCC
1% Duty Cycle
tr, tr £ 100 ns
RS at 0 V or VCC
This test is conducted to test survivability only. Data stability at the R output is not specified.
DUT
CANH
D
0V 60 W ± 1%
Rs CANL
VI
+
VO 15 pF ± 20%
_
VCC
0.7 VCC
VI
0V
VOH
27 W ± 1%
CANH
D
VI
CANL 27 W ± 1% 50 pF ±20%
VOC
RS
VOC(PP)
VOC
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤
6ns, tf ≤ 6ns, ZO = 50 Ω.
DUT
CANH
D
VI 60 W ± 1%
10 kW or 100 kW ± 5%
RS CANL
_ VRs +
R
+
VO 15 pF ± 20%
_
VCC
D Input 50%
0V
tLoop2 tLoop1
VOH
0.7 Vcc
R Output 0.3 Vcc
VOL
IOS
D CANH
0 V or VCC
Rs CANL Vin –7 V or 12 V
I OS(SS)
I OS(P)
15 s
0V
12 V
Vin
0V
or 10 s
0V
Vin
–7 V
CANH
R
VI
CANL CL = 15 pF
(see Note A) 1.5 V VO
(see Note B)
3.5 V
2.4 V
VI
1.5 V
tp(sb)
VOH
VO
0.3 VCC
VOL
A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr ≤
6ns, tf ≤ 6ns, ZO = 50 Ω.
B. CL includes instrumentation and fixture capacitance within ±20%.
Figure 21. Receiver Propagation Delay in Standby Test Circuit and Waveform
5V
R2±1%
R1±1%
CANH +
R
VID
CANL – Vac
R1±1%
VI
R2±1%
VID R1 R2
500 mV 50 450
900 mV 50 227
12 V
VI
–7 V
A. All input pulses are supplied by a generator having the following characteristics: fIN < 1.5 MHz, TA = 25°C, VCC = 5 V.
B. The receiver output should not change state during application of the common-mode input waveform.
8 Detailed Description
8.1 Overview
The SNx5HVD251CAN bus transceiver is compatible with the ISO 11898-2 High Speed CAN (Controller Area
Network) physical layer standard. It is design to interface between the differential bus lines in controller area
network and the CAN protocol controller at data rates up to 1 Mbps.
VCC (3)
Undervoltage
SLOPE
CONTROL and
VCC (3)
RS
Overtemperature MODE LOGIC
Sensor VCC/2 VREF (5)
Vcc (3)
CANH
D Driver
CANL
1
D
RS 8
7
4 CANH
R 6 CANL
NOTE
Silent mode may be used to implement babbling idiot protection, to ensure that the driver
does not disrupt the network during a local fault. Silent mode may also be used in
redundant systems to select or de-select the redundant transceiver (driver) when needed.
10kΩ
to
RS 100k Ω
D 1 8 TMS320LF2407
GND 2 7 CANH
VCC 3 6 CANL
R 4 5 VREF
Table 3. Receiver
DIFFERENTIAL INPUTS [VID = V(CANH) - V(CANL)] OUTPUT R (1)
VID ≥ 0.9 V L
0.5 V < VID < 0.9 V ?
VID ≤ 0.5 V H
Open H
D Input R Output
Vcc Vcc
100 kW
1 kW 15 W
Input Output
9V 9V
110 kW 9 kW 110 kW 9 kW
45 kW 45 kW
Input Input
40 V 9 kW 40 V 9 kW
Vcc Vcc
Output
40 V
+
Input
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
CANH
3
Vdiff(D)
2
Vdiff(R)
CANL
1
Time, t
Recessive Dominant Recessive
Logic H Logic L Logic H
Figure 26. Bus States
CANH
VCC/2
RXD
CANL
The HVD251 CAN transceiver is typically used in applications with a host microprocessor or FPGA that includes
the link layer portion of the CAN protocol. The different nodes on the network are typically connected through the
use of a 120-Ω characteristic impedance twisted pair cable with termination on both ends of the bus.
The ISO 11898 standard specifies a maximum bus length of 40 meters and maximum stub length of 0.3 meters
with a maximum of 30 nodes. However, with careful design, users can have longer cables, longer stub lengths,
and many more nodes on a bus. (Note: Non-standard application may come with a trade-off in signaling rate.) A
bus with a large number of nodes requires a transceiver with high input impedance such as the HVD251.
The Standard specifies the interconnect to be a single twisted-pair cable (shielded or unshielded) with 120-Ω
characteristic impedance (Zo). Resistors equal to the characteristic impedance of the line terminate both ends of
the cable to prevent signal reflections. Unterminated drop-lines connect nodes to the bus and should be kept as
short as possible to minimize signal reflections.
Connectors, while not specified by the ISO 11898 standard, should have as little effect as possible on standard
operating parameters such as capacitive loading. Although unshielded cable is used in many applications, data
transmission circuits employing CAN transceivers are usually used in applications requiring a rugged
interconnection with a wide common-mode voltage range. Therefore, shielded cable is recommended in these
electronically harsh environments, and when coupled with the –2-V to 7-V common-mode range of tolerable
ground noise specified in the standard, helps to ensure data integrity. The HVD251 extends data integrity beyond
that of the standard with an extended –7-V to 12-V range of common-mode operation.
NOISE MARGIN
900 mV Threshold
RECEIVER DETECTION WINDOW 75% SAMPLE POINT
500 mV Threshold
NOISE MARGIN
ALLOWABLE JITTER
An eye pattern is a useful tool for measuring overall signal quality. As displayed in Figure 28, the differential
signal changes logic states in two places on the display, producing an eye. Instead of viewing only one logic
crossing on the scope, an entire bit of data is brought into view. The resulting eye pattern includes all effects of
systemic and random distortion, and displays the time during which a signal may be considered valid.
The height of the eye above or below the receiver threshold voltage level at the sampling point is the noise
margin of the system. Jitter is typically measured at the differential voltage zero-crossing during the logic state
transition of a signal. Note that jitter present at the receiver threshold voltage level is considered by some to be a
more effective representation of the jitter at the input of a receiver.
As the sum of skew and noise increases, the eye closes and data is corrupted. Closing the width decreases the
time available for accurate sampling, and lowering the height enters the 900-mV or 500-mV threshold of a
receiver.
Different sources induce noise onto a signal. The more obvious noise sources are the components of a
transmission circuit themselves; the signal transmitter, traces & cables, connectors, and the receiver. Beyond
that, there is a termination dependency, cross-talk from clock traces and other proximity effects, VCC and ground
bounce, and electromagnetic interference from near-by electrical equipment.
The balanced receiver inputs of the HVD251 mitigate most sources of signal corruption, and when used with a
quality shielded twisted-pair cable, help meet data integrity.
VCC
3
RXD R (4)
TXD D (1)
CANL (6)
Optional:
Terminating
GND (2)
Node
Node n
Node 1 Node 2 Node 3 (with termination)
MCU or DSP
MCU or DSP MCU or DSP MCU or DSP
CAN
CAN CAN CAN Controller
Controller Controller Controller
SN65HVD257 CAN
SN65HVD251 CAN SN65HVD1050 CAN SN65HVD233 CAN Transceiver
Transceiver Transceiver Transceiver
RTERM
RTERM
RTERM/2
CAN CAN
RTERM
Transceiver Transceiver
RTERM/2
CANL CANL
9.3.1.1 Introduction
The SNx5HVD251 CAN transceiver is a 5-V CAN transceiver that meets or exceeds the specification of the ISO
11898 standard for applications employing a controller area network.
The CAN driver creates the differential voltage between CANH and CANL in the dominant state. The dominant
differential output of the HVD251 is greater than 1.5 V and less than 3 V across a 60-Ω load as defined by the
ISO 11898 standard. Figure 33 shows CANH, CANL, and the differential dominant state level for the
SNx5HVD251.
A CAN receiver is required to output a recessive state when less than 500 mV of differential voltage exists on the
bus, and a dominant state when more than 900 mV of differential voltage exists on the bus. The CAN receiver
must do this with common-mode input voltages from –2 V to 7 V.
11 Layout
NOTE
High frequency current follows the path of least inductance and not the path of least
resistance.
Design the bus protection components in the direction of the signal path. Do not force the transient current to
divert from the signal path to reach the protection device.
An example placement of the Transient Voltage Suppression (TVS) device indicated as D1 (either bi-directional
diode or varistor solution) and bus filter capacitors C5 and C7 are shown in Figure 34.
The bus transient protection and filtering components should be placed as close to the bus connector, J1, as
possible. This prevents transients, ESD and noise from penetrating onto the board and disturbing other devices.
Bus termination: Figure 31 shows split termination. This is where the termination is split into two resistors, R5
and R6, with the center or split tap of the termination connected to ground via capacitor C6. Split termination
provides common mode filtering for the bus. When termination is placed on the board instead of directly on the
bus, care must be taken to ensure the terminating node is not removed from the bus as this will cause signal
integrity issues if the bus is not properly terminated on both ends.
Bypass and bulk capacitors should be placed as close as possible to the supply pins of transceiver, examples
C2, C3 (VCC).
Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to minimize
trace and via inductance.
To limit current of digital lines, serial resistors may be used. Examples are R1, R2, R3 and R4.
To filter noise on the digital IO lines, a capacitor may be used close to the input side of the IO as shown by C1
and C4.
Since the internal pull up and pull down biasing of the device is weak for floating pins, an external 1-kΩ to 10-kΩ
pullup or pulldown resistor should be used to bias the state of the pin more strongly against noise during
transient events.
Pin 1: If an open-drain host processor is used to drive the D pin of the device an external pullup resistor between
1 kΩ and 10 kΩ should be used to drive the recessive input state of the device.
Pin 5: is VREF output voltage reference, if used, this pin should be tied to the common mode point of the split
termination. If VREF is not used, the pin can be left floating.
Pin 8: is shown assuming the mode pin, RS, will be used. If the device will only be used in high-speed mode or
slope control mode, R3 is not needed and the pads of C4 could be used for the pulldown resistor to GND.
D R1 1 8 R3 RS
C4
C1
GND
C5
GND 2 7 R5
U1
D1
J1
SN65HVD251 VREF C6
C2
C3
VCC R6
C7
3 6
R R2 4 5 R4
Figure 34. Layout Example Recommendation
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 24-Aug-2018
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
SN55HVD251DRJR ACTIVE SON DRJ 8 1000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -55 to 125 SN55
& no Sb/Br) HVD251
SN65HVD251D ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 VP251
& no Sb/Br)
SN65HVD251DG4 ACTIVE SOIC D 8 75 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 VP251
& no Sb/Br)
SN65HVD251DR ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 VP251
& no Sb/Br)
SN65HVD251DRG4 ACTIVE SOIC D 8 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 125 VP251
& no Sb/Br)
SN65HVD251P ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 125 65HVD251
& no Sb/Br)
SN65HVD251PE4 ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 125 65HVD251
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 24-Aug-2018
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
• Automotive: SN65HVD251-Q1
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Jun-2016
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 15-Jun-2016
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
4214825/C 02/2019
NOTES: (continued)
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EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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