G365 SCHENME I8EVBMML33

USN

Third Semester B.E. Degree Examination, Aug. Sept. z0-0

Analog Electric Circuits

Time: 3hrs Max. Marks: 100
NOe Answer any FlV'E full questions, choosing ONE full question fom cach mue

Module-1
d Dene operating point. Discuss the various noint locations within limt of ogpera
transistor. (08 Marks)
.ENplam load line of Fixed bias coniguration of BJT with variation of change m lg. K; dtu
Vee which varies
.
Q-point with neat sketches. (08 Marks)
Dcermime the
lsq and leo VcEQ. VB. V¢ and Vac for Fixed Bias contiguration ot Fig
Q

OMF
loE Pso
Fig Q1(c) (04 Marks)

OR
a. EXplam and derive necessary DC biasing equations of vo tage Divider Bias of BJT for Exact
and Approximation analysis with relevant diagram. (12 Marks)
b. Obtain DC bias equations of FET using self-bias configuration with aid of neat sketeches.

(08 Marks)

Module-2
3 a. Discuss the process of obtaining re model equivalent for transistor. (10 Marks)
b. Explain and derive the z, Z, and Ay of CE emitter bias configuration using re model with
relevant figures. (10 Marks)

OR
a. For the voltage Divider Bias network shown in Fig Q4(a), find the following :
9e i) 2, (t= ol) iv) A, (o=od) repeat parts of i) through iv),ifto =5OK
and compare result.
pYe 2 2 V

le
5tK zR R6K
N

B90

Fig Q4(a) (10 Marks)

b. Discuss the effect of R, and Ri, of BJT with complete r, model (10 Marks)

l of 2
 MV/BM/MI.33
Module-3
1o) Conlguratinn
configurat on using
5 bta e expressions for Z, Z and A, of
source
with
relevant sketches. volage D d e r configurat (19 Marks
z,, Zo
and Av of
b. and derive expression for
plain
with aid of neat sketches. (10 Mars
OR
stage CE
ofBJT amplifier of Single amplifier. (12
am.

6 Explain the
Oblain
low
the input
frequency response
and output
capacitance
using Milleretfect analysis.
(% MarMarks
koy
Module-4
sketches.

Discuss the class B

amplifier
circuit with
neat

coupled push-pull
with neat figure (% Marksy
ampliiier far
a.
b. Explain the
operations
transformer
of
Transformer
class A
coupled class led
A amplifier 1or a
supply of 12
ofa 2V.
and
=

Calculate the efficieDcy ii) VP)

c.
12V
= i) VP)
6V =

(06 Marksy
Output of i) Ve
:
OR
class - A amplifier.
Explain the
operations of
series-fed
coupled
Class with neat dagram. (12 Marksy
A amplifier with ncns

(08
8
b.
a.
Discuss the
function of
Transformer
Marks
Module-5
in general.
offeedback
concept
(06 Marks)
Describe the concept
9 a.
effect of negative
feedback.
circuit. (06 Marks)
bb. List the
Feedback

FET based voltage

series (08 Marksy
c. Explain

OR
oscillation.
for sustained
(06 Marky
condition
oscillator with
neat díagram
10 a.
a. Explain
BJT based crystal
oscillation using UJT with neat dias
(07Marks
b. Explain the
obtain the relaxation diagram. (07Marks)
Discuss how to
c.

2 of 2
 CEGS SCHEME
USN 17EI/BM/ML33

Third Semester B.E. Degree Examination, Aug./Sept.2040

Analog Electronic Circuits
Time: 3 hrs.
Max. Marks: 100
oe: Answer any
FIVE full questions5, choosing ONE full question from each modue.

12erve the expression for voltage gain, Z

Module-1
and Z, of a voltage divider bias circuit usig'*
model. (08 Marks)
D.
Explain the need for cascading of amplifiers. Also write the circuit of two-stage KC
amplifier. COuy
(06 Marks)
CWrite the cascode amplifier circuit and (06 Marks)
explain the features.
OR
a Derive expressions for Z, Z, and Ay, for a Darlington emitter follower circut. (10 Marks)
. Derive expression for
Zi, Z, and Ay using BIT (10 Marks)
approximate hybrid model.

a. Module-2and operation of n-channel JFET.

With the neat figures, explain the construction (10 Marks)
D.Obtainthe transfer curve from the drain characteristics with the relevant equatiOn. (l0a

OR
4 a. Draw and explain the
construction
b.List the difference between
of Pchannel D-MOSFET. (08 Marks)
JFET and MOSFET. (04 Marks)
C. For circuii shown in
Fig.Q.4(c), caleulate Ib, Vos.
Vo, VDs and Vs of votage divider circuit.
(08 Marks)
VopV

2ok

pss l2mA

-4
lo

Fig.Q4(c)
Module-3
5 a. Write the a.c. equivalent eircuit för fixed bias JFET configuration and determine Z, Z, and
Av. (10 Marks)
b. Derive the expression for Z, Z, and A, for souree follower JFET amplifier. (10 Marks)

OR
6 a. Discuss the factors that affects the low frequency response of a BJT-CE amplifier. (10 Marks)
b. Describe Miller effect and derive an equation for miller input and output capacitances.
(10 Marks)

of 2
 17EI/BM/M
Module-4
briefly. lifier is
is 259%
25%.
(06 Mark
Discuss
them
power
ampli

pown
(10 Mar
class A and a wer supply s
classified?
fed, 1oad
amplifiers to a 16-s2e
of'serics

a. How power
cefliciency signal fficiency.
clliciency.
lf
(04 Mark
Show that the
maximum
20-V peak nd
and
circuit circuit

bb. providing a power

or a class B amplifier
ut
power, outpul py
C.

30V, determine the input

Vcc
OR

8 a. Explain with circuit diagram: circun.

(12 Marks
methok
Transformer coupled push-pull
tnrec-point

usng

1) Complementary symmetry circuit

and derive an
expression (08 Marks
distortion
b. Explain second harm

diagram
n
explain the types c
Module-55 the block
With (10 Marks
9 a.
What are the advantages of negative feedback?
feedback connections,
b. Explain the following with circuits:
i) Wein Bridge oscillator (10 Marks)
ii) Unijunctjon oscillaltor

OR
in an oSClatO
(07 Marks
10 a. criterion? Explain how oscillations starts 40KQ whil
Daknausen
A phase shift oscillator is to be iesigned with FET having gm
=
5000us, ra hile
value of C RD
and R to have
the resistance in thefeedback circuit is 9.7KQ. Select the proper
the frequency of oscillat ions as SkHz.
(07 Marks)
c. Explain the operation of FET Hartly oscillator.
(06 Marks)

* * **
 GBGS SCHEME
17E BM33

Third Semester B.E. Degree Examination. Dec.2019/Jan.202

Analog Electronic Circuits
Time: 3 hrs. Max. Marks: 100

Nore: Amswer any FIV E ful questions. choosing ONE fall question from each module.

Module-1
1a. Draw the circuit of common emitter voltage divider bias configuration and its T
(10 Marks)
Obtain an expression for Z, Z, and A, of the circuit.
b. Mention the necessity of cascading the systems and caseade connection of transistor. Dia
(10 Marks)
Darlington connection of BJT transistor.

OR
6.SKI.
divider biased amplifiers has V 20V, Ri =220KQ, R 56KO. Rc
=
=

2a. A vo ltage =

RE 2.2K2. The silicon transistor used has B 180 and ro = 70K. Find re. Z, Zo and A
(08 Marks)

model for BJT common Emitter

b. Considering two port system, obtain hybrid equivalent (12 Marks)
configuration. Also determine equation for h-parameters.

Module-2
characteristics with Vas =0V and VDs ofsome
3 a. With diagram, illustrate the construction and (10 Marks)
value of Junction Field Effective Transistor (JFET).
positive Q.3(b). Given that
b. Determine the levels of Voso. Ibo and Vps for
the network shown in Fig
(06 Marks)
Ipss =10mA, V, =
-8V. Sketchthe Q-point. Voo 16 V

Ro 2E

).

Vos 2V

Fig.Q.3(b) (04 Marks)

C. With diagram, explain CMOS-basics
OR 3.3KO.
and Vpp 20V with Rp
=
=

Ioss 8mA, V, -6V

=
=

4 a. For JFET self-bias network having (06 Marks)

1KO, determine Voso and Ipo.
RG IMQ and Rs = n-channel depletion type
MOSFET. (06 Marks)

D. Explain the construction

and operation of with necessary
and analyze ts operat1ion
C. Draw JFET voltage-divider configuration (08 Marks)

equations.

T of2
5a. The fixed-bias
IDo
configuration of JFET had
Module-3
an operating point defined by .
5.625mA, with Ipss = 10mA and Vp= = -8V, The network has R. GSQ
17EAIBM
Ra= IM RD
with VpD = 20V and Vea = 2V. The value of Yos = 40us. DetermiK a
Z and Ay ignoring effects of ra. nine gm, t
(06 M
Derive expressions for Z Z, and A, for JFET amplifier with self-bias configurs6 Mar
equivalent model.
Derive an expression for Miller Input capacitance and Miller output capacitanc (06 Mar
device. tance of ana
acti
(08 Mark
OR
a. With circuit diagram of BJT amplifier. Discuss the low frequency response
nse and
and the
or capacitor Cs, CE and Cc connected across the active device.
D.
Deternmine the high-cut-off (10 impa
Mar
frequencies for the network of Fi1g.Q.6(6) using
ng parame
Co 0.01uF, C¢
=0.5uf, Cs 2uF, 10K2, Rg IM2, Ro 4.7 .7KO, Rs k
RI2.2K2, Ip =8mA, V, =4V, raRsigo, VDD 20V, Cgd 2pt,
= = = =

Cgs 4pf, Ca, (0 5 =

Cw 5pF and Cwo =6pF.

VoD (10 Mar
Ro
Cqd

Fig.Q6(b)
Cs

7a. Draw the circuit

of
Module-4
Derive series-fed
class A power amplifier and
explain the DC and AC operatiot
b.
expression for its maximum efficiency.
Calculate the efficiency
of a class B (10 Mark
4Q load with amplifier for a supply voltage of Vcc 22V =

i) VLp) 20V
peak output voltages of. driving
11) VLp) 10V. Also find
input and output power. (10 Mark
8 a. With circuit, OR
explain the
Also explain cross-over working of
b. distortion. complementary-symmetry
class-B push-pull
amplifie
Why distortion occurs in power (10 Marke
for an output amplifier circuit? Calculate harmonic distortion
signal having fundamental
harmonie amplitude of amplitude of 2.5V, second, third componen
and fourt
Distortion. 0.25V, .1V and 0.05V
respectively. Also calculate Total Harmon
(10 Marks
9 a. State and explain Barkhausen Module-5
criteria for sustained oscillation.
b. Draw the circuit
diagram of BJT Hartley oscillator and (06 Marks
expressions for frequency of oscillations and condition on explain its operation. Write t
C.
Design Wein bridge oscillator for a hte.
0.01nF. frequency of oscillation of 4kHz using a (10 Mark
capacitor
(04 Mark=
10 a. Name four basic OR
types of connecting the feedback
open loop (A) and closed signal. Draw block diagram along wi
b. loop gain (A1) and feedback factor
(B).
Explain the working of transistor phase shift oscillator. (08 Mark
C. Draw the circuit (06 Marke
diagram of Unijunction oscillator and explain its
expressions for frequency of oscillations. operation. Writ
(06 Marks
**** *
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 3 sEM EIE
USN
GBCS SCHEME 17E/BM33

Third Semester B.E.

Degree Examination, June/July 2019
Analog Electronics Circuitss
Time: 3 hrs. Max. Marks: 100

Note: Answer any FIVE full

questions, choOSing
ONE full question from each
module
Module-1
1a. Draw the circuit of
common emitier voltage divider bias conigua
Obtain expression for Zi, Zo (10 Marks)
and Ay of the circuit.
D.rortne emitter follower ciruit shown in Fig.O1b). determine rea, Zi, Zo and Av
2v

0-27-
220K

V P:100,
104F
E V
3:3k

Fig.Q1(b) (04 Marks)

C.
Explain the need for cascode systems.
OR
2 a. Explain the features of cascade connection and Darlingtonconnection with circuits
(08 Marks)
b. Obtain expression for Z, Z and Av for BJT fixed bias configuration using approximate
hybrid equivalent model. (08 Marks)
C. Compare hybrid model and Ie model for BJIT. (04 Marks

Module-2
3 a. Explain the construction and characteristics ofjunetion field effect transistor. (10 Marks)
b. Draw and explain the JFET self-bias configuration with necessary equations and Q-point of

operation. (10 Marks)

OR
4 a. Explain the construction, operation/and characteristics of n-channel depletion type
MOSFET. (10 Marks)
b. For the JFET circuit shown in Fig.04(6), determine Vaso, lpo, Vos, V», VG and Vs. Also
sketch the transform characteristic and indicate Ipo, Ipss, Voso and Vp. (10 Marks)

6V

D s s 10 mA

Vp-8v
Fig.Q4(b)
1 of 2
5 a.

b.
put
he JFET source
Module-3
Draw the JFET fixed bias configuration and its AC equivalent circuit. Oht:
of
impedance, output impedance and voltage gain the circuit.
in
follower shown in Fig.Q5(b) has the following parameter
1EAIB
express
(19 Mar
lo 4.56mA, Ioss = 16mA, Vp = -4V and Yos254s, Determine gm, ra
Td,
O-2363
i, TAy andN
(10 Mark
D:bSF
O-0SF
H
Vi Z JM 2-2kn

Fig.Q5(b)

6 OR
a.
Explain the impact of capacitors Cs, Cc and CE on the low freque
amplifier. response of B
b. Derive expression for Miller input capacitance and output capacitance of an actiar
C. An
amplifier consists of three identical stages in cascade. The bandwidth of
devi
extends from 20Hz to 20KHz. Calculate the bandwidth overallar
of individual
stage. amplifi
(04 Mark
a. Draw the circuit and Module-4
derive an
input-output signal variation of series fed class A power amplifo.
D.
expression for its maximum efficiency. a
A class B (10 Mark
power amplifier supplies a 18V peak signal to a 16s2 l0ad
supply of Vcc 24V. Determine the peak load current, DC current, using a DC no
=

pow
power and circuit input power, ot
efficiency. tp
(10 Mark
8 OR
a. Derive an
expression for the maximum efficiency of a class B
b.
Explain the working of a transformer coupled class B
amplifier. (06 Mark
diagram. push-pull amplifier with a neat cir
C. Define harmonic distortion. Calculate the (08 Mark
harmonic distortion
signal having fundamental amplitude of 2.5V, second harmonic components for an outd
harmonic amplitude of 0.1V and fourth harmonic amplitude of 0.25V, Thi
total harmonic distortion. amplitude of 0.05V. Also
determine t
(06 Mark

9 Module-5
a.
Mention the effects of negative feedback on amplifiers.
b. Explain the working of a (04 Mark
BJT phase shift oscillator with a neat circuit.
C. A (08 Mark
crystal has L =
0.4H, C =

0.085pF, Cm 1pF and R SKQ. Find

=
=

the series resona

frequency, parallel resonant frequency and Q-factor of crystal. (08 Mark
OR
10 a. Sketch the four basic types of connection the
feedback signal indicating the relevant
forward and feedback path gain. signa
b. 08 Mar
Explain the working ofa BJT Hartley oscillator and derive expression for its frequency
oscillation.
(08 Mark
c. Design a Wein bridge oscillator to generate a frequency signal of using 4KHz capacitors
0.01F each. (04 Marki
* ** **

2 of 2
 Semester B.E.
Degree 15E/BM/ML33
Third
Examination,
Analog Electronic JunelJuly 2019
Circuits
hrs
Note: swer any FIV full Max. Marks: 80
ONE full questions,
question from each module.choosing
Module-1
Nhat
is model? divider
Draw voltage divider bias circuit for
BJT and its
ain expression for4, Za und Av.
network shown in Fig.C
re
equivalent circuit and
l o r the determine: i) Z, i) 7a iü) Av (10 Marks)
vbrid equivalent eircui iven: hie= 120, hie= iv) A, with the
help of
1.175k2 and hoe =
20uA/v. (06 Marks)
330kL 8

Fig.Q1(b)
OR
Wth the help of two-port system Obtain an expression for
hybrid cquivalent circuit. h-parameters and draw complete
h e CE emitter bias contiguration of BJT and with the (06 Marks)
help of its
derive an expressions for 1) Z, 1) Z411) A (Assume unbypassed). r equivalent circuit
Mention the features ofcascadeconnection. (08 Marks)
(02 Marks)
Module-2
a . Compare BJT with
FET
Draw the drain and transfer characteristic of an FET, and comment n characteristies.(03 Marks)
(06 Marks)
eDiscuss the construction of P-channel depletion type MOSFET and brief its operations.
(07 Marks)

OR
aDetermine the following for the network shown in Fig.Q4(a).
i) lboand Voso (Q-point and Graph) i) Vp ii) Vs iv) Vos VpG
Given, Ipss-8mA and V,=4V (10 Marks)
pp 16 V
M
2-410HE
7AF
70K

Fig.Q4(a)
type MOSFET and sketch
its
DISCuSs the basic construction of p-channel enhancement (06 Marks)
transler and drain characteristics.
1 of 2
 Module- ith the help of its eg
15EAIBMA
with

5 a. Draw the nmon-drain

configuration

Av.
of FET, uivalent cir ohtd
Cxpressions for i) Z i) Zo iii)
09 Ma
DObtain an expression for lower
cutoff frequency, I 2t(R+ R,)C of BJT amp
frequeney response).
OR
of FET amplifier
and obtain the
6 a. Analyse the high frequency response relate paramett
b. equations.
For the network shown in Fig.Q6(b), determine i) Bm in) ra ii) Z;
Zi iv)
iv) z.Zo with (08 Marl
and
effects of ra v) Av with ra= o VoD 2oV vwithd
Given 33n
VasQ-2.6V
Ipo 2.6mA
Ipss 8mnA
V=-6V IM
Yos 20us
Fig.Q6(b) (08 Mark
Module-4
7 a. Classify the power amplifiers based on operating cycle and mention their ntion
their powe power
b. (06
For a class B amplifier providing a 20-V peak signal to a 162 load (sneakerl aMar
etticiend
supply of Vcc=30V. Determine the input power, output power and circuit efficiena4 pow
ciency.
C. Draw the block diagram of class D amplifier ánd brief its working. (06 Mark
(04 Mark
OR
8 a. With the help ofrelevant waveform obtin expression tor second harmonic distortion D,.
b. Draw the circuit of series fed çlass A large-signal amplifier and discuss the (06DeMark
L
operation, ACoperation and hence obtain an expression for maximum efficiency, cag
C.
Comparé small-signal amiplifier with large signal amplifier.
(02 Marke

9 a. Draw the four basic ways of

Module-5
connecting the feedback signal in amplifiers and name thei
with input and output signal and
transfer ratio.
b. Mention the
C.
obtain by providing a negative feedback in amplifiers. (06
improvements
Draw the circuit of FET
Mark
(04 mark
phase shift oscillator and explain its operation with
equations.
(06 Mark

10 OR
a. Mention Barkhausen criterion for
oscillation and explain with block
implementation. diagram for th
With circuit diagram explain the working (04 Mark
of transistor
frequency. colpitts oscillator with expression f
C. With circuit and waveforms (06 marks
explain the operation of unijunction transistor. (06 Mark
** * * *

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