(Please write your Enrollment Enrollmcnt No.

Number)
ENIDTERM EXAMINATION
(CBCSXSUBJECTIVE TYPE)
Semester: 1"
Coursc Name :<B. Tech. ECE-AI>,
(March, 2023)
Subject: Analog Electronics
Subject Code: BEC 101 Maximum Marks :60
Time :3 Hours
oe: Tis compulsory, Attempt one ouestion cach from the Units I, 1, IM &IV.
Q1 (2.5*8=20)

(a) Explain the ellect of temperature on semiconductors

(b) What is a mass acion law? level
of 0-7 ev, delermine the position of fermi
(c) ror an intrinsic semiconductor with encrgy gap
at 300K if nn, =6 m,
(d Explain the Ebers- Moll Model.
circuit for each topology.
(e) Give four topologies to yicld negative feedback. Draw
(0) What are the various modcs of operation of a transistor? Explain each region.
(g Why is silicon preferred in semiconductor devices over gemanium?
(h) Write a short note on Ficld effect transistors.

UNIT-1
(10)
Q2 What is Zener diode? Explain the Zener breakdown and applications of Zencr
diode. For the given circuit a) calculate VL, VR, 1Z and P2. b) repeat a) with RL
= 3KQ.

+ Ve

I6V 10 v2A
Pu 30 mW

Explain the working of a PN diode in Forward and Reverse bias condition. (10)
Q3
Explain properly using circuit diagram, current equation andwaveforms.
UNIT-I1
What is biasing? Determine the dc bias voltage VcE and the current lç for the (10)
voltage divider configuration shown below:

+22 V

3.9 A2
50 uF

Q5 Explain the current components in a PNP transistor with a help of a suitablc (10)
diagram.
UNIT-Iu

Q6 Write a short note on Thermistor and Schottky diodes. (10)

Q7 Draw the circuit of two stages R-C coupled transistor amplifier and explain its (10)
working of it
UNIT-IV
Q8 Explain the working of the JFET amplifier circuit. Also explain the
(10)
characteristics and operating conditions of JFET.
Q9 Explain tlhe working of depletion type MOSFET. Also derive Shockley's
equation for drain current. (10)
2
(Please write vour Enrollmnent Enrollment No.
Number)
End-Term Examination
(CBCS)(SUBJECTIVE TYPE)(OffLine)
Course Name: B.Tech. (ECE-AI), Semester:1" Sem
(Feb-March, 2023)
Subject Code: BEC-101 Subject: ANALOG ELECTRONICS
Time :3 Hours
Maximum Marks :60
NOte: Q. 1 is compulsory. Attempt one question each from the Units I, II, I| & IV.
Q1
(2.5*8=20)
(a) Draw andexplain the energy band diagram of PN junction diode.
(b Draw the output characteristics of CE, CB, CE configurations of
transistor.
(c Explain why BJTs are called bipolar devices while FETs are called
unipolar devices.
(d) What is a Darlington transistor? Discuss its salient features.
(e) Explain the two-transistor analogy of an SCR in brief.
(f) What is thermal runaway? Explain how the selection of operating point
affects thermal stability.
(e) What are the various coupling schemes used in cascade
(h) amplifiers?
What is clipper? Differentiate between positive clipper and
clipper. negative

UNIT-I
Q2 (a) Explain how transition capacitance Cr varies
with reverse (10)
voltage.[4|
(b) Show that the Zener diode can be used as a
with suitable example.[6] voltage regulator
Q3 (a) Draw D.C load line for a CE transistor.
Explain the reason for (10)
selecting Qpoint in the middle of the D.C load line. Also
discuss the reasons which lead to shift in Q point. [5]
(b) In a CE transistor amplifier circuit, the bias is
bias. If the various parameters are Vcc = 12V,
provided by self
R=10k2,
R=Sk2, Re=Ik2, RE=2ks2, and B=100, find
() the coordinates of the operating point and
(ii)the stability factor, assuming the transistor to be silicon. (5]
UNIT-II
Q4 Derive the equations for voltage gain, current gain,
and output impedance for a BJT in input impedance (10)
CE configuration using low
frequency h-parameter model.
Q5 Drawthe cascode amplifier circuit and
gain, current gain, input impedance and
derive expressions for voltage (10)
output impedance.
UNIT-1||
Q6 Discuss the effect of negative feedback on the
characteristics: following amplifier (10)
(i) Voltage gain (ii)
Bandwidth (ii) Non-linear distortion (iv) Input
impedance (v) Output impedance.
PTO
 Q7
With the help of relevant schematic diagram, explain the operation (10)
principle ofaUJT with reference to its V-l characteristics. Also explain
how a UJT can be employed in oscillators owing to its ncgative
resistance property.
UNIT-IV
Q8 Draw and explain the drain and transfer characteristics of an (10)
enhancement and depletion type MOSFET.
Q9 Discuss the different types of biasing methods for JFET. Also (10)
explain how voltage divider bias can be used for both MOSFET as
well as for JFET.
(Pleae rite yur tnrdtmant Nunber)
End-Term Evaminatin (Pegsar and Reappear)
(CHCS)(SUBSECTVE TYPE)(OffLine)
Course Name: B.Tech. ECEAI, Sernester:1 Sem.
(December, 2023)

|Suthjet Code BEC01 uhjea: Analog Electuonks

Time : Murs
ote0 1 is ampulry. Atenpt one question each fromtheUnits i, W, &N
01 (25220)
(a) Erplain the effet f ternperature
ernidurs,
(o) What are lener diodesand why are they alledvohtage rezulators?
Calslats the onductfty and resistilityof pure Ge st 300 K wheren, is 2.5 1
10, electron rnobifity is 3000 and hole rnobility is 1200.
(d) Give onparison of CB, CE, CC amplifiers on the basis of input resástane,
outputresístane, urrent yain, voltage yain and power yain.
(e) What are advantayes of negatíve feedback over psitive feedback?
How drift srrents are different fron diffusson currents. Explain with árasit
diagrarn ofa transístor.
Give advantages of Field Effect Transistor (FET) ver Bipolar Junction
Transistor (BJ).
(h) Differentíate arnong enhanCernent ode and depletion rmodes of MOSFET.
UNIT4
02 Explain the working of Common Base configuration of transistor for (10)
active, ut-off and saturation regions of operations ith required V4
charateristíc waveforrns.
03 What is thermal stability? Why do we use stabilization techniques? (10)
Discuss stabilization techniques used in amplifiers.
UNIT-41
04 Draw the hybrid equivalent model circuits of CB, CE and CC and give the (10)
requíred hpararnete cquations for cach model.
Use hiez2 KO, hfe=50, hre=2 %10%, hoe = 20 %10 A/v. Find AFl/, Ag= (10)
V/Vs, Rieff, Ro, Ro' from the circuit given in Figure1.

I,

lor Ky

Figure1
Page 1 of 2
 UNIT-M
Q6 Give cdassitication of negative feedback anmplifiers and discuss each (10)
onfigurationwith overall gain using feedback and their input and output
impedance considerations.
Q7 Give detailed working of Unijunction Transistor (UJT) with suitable (10)
diagram, symbols, operations, characteristics, advantages, disadvantages
and areaof applications.
UNIT-IV
QS Explain the working of n-channel JFET. Give detailed diagram of drain
(10)
characteristics and discuss for various gate to source voltage values.
Q9 Sketch a p-channel enhancement type MOSFET and explain its
with the help of gate and drain characteristics waveforms. working (10)
(Please write your Enrollment Number) Enrollment No.

Supplementary Examination
(CBCS)(SUBJECTIVE TYPE)(OffLine)
Course Name: B. Tech., Semester: I
(January 2024)

Subject Code: BEC 104 Subject: Digital Electronics

Time :3 Hours Maximum Marks :60
Note: Q. 1 is compulsory. Attempt one question each from the Units I, I, 1&IV.
Q1 (2.5*8=20)
(a) Simplifythe following Boolean Expression, Y= (AB +C) (AB +D)
(b) Differentiate between Positive logic and Negative Logic, with example
(c) What are PRESET and CLEAR inputs in the Flipflops. Discuss their operation.
(d) Covert the Gray code 1001011 to binary
(e) Draw the Internal Circuitry for RS flip flop using only NAND gates. State its truth
table to0.
(f) State the Excitation Table for JK flip-flop.
(B) Differentiate between ROM, PAL and PLA.
(h) Convert the Dflip flop to Tflip flop.
UNIT-I
Q2(a) Obtain a reduced expression using K-maps and realize the minimized (7+3)
function using NOR gates only
F1 (A, B, C, D)=X m (0,1,2, 5,7,8,9, 10,13, 15)
(b) Prove that AB + ABC + AB' = A
Q3 (a) An equality detector gives the output Y = 1, if both the inputs A and B (7+3)
are either 1 or 0
(i) Construct the truth table
(ii) Write the Boolean expression of Y
(ii) Implement the circuit using NAND gates only
(b) Convert the following expression in canonical SOP form.
Y=A+ BC + ABC
UNIT-I|
Q4 (a) Construct a3-bit Twisted Ring Counter using the JK flip flops. (4+6)
(b) Implement the following Boolean function using 8:1 multiplexer. F(A, B,
C, D) = ) m (2,4,5,7, 10, 14)
Q5 With the help of appropriate waveforms, explain the functioning of MOD-8 (10)
Down Ripple Counter using positive edge triggered flip flops.
UNIT-II|
Q6 A5 bit DAC produces Vo = 1.4 Vfor a digital input of 00111. Find (a) its % (10)
resolution, (b) step size (AV), (c) Vo for digital input of 11000 and(d) full
scale analog voltage
Q7 Using J-K flip-flops, design a synchronouscounter that has the following (10)
sequence ....0’ 2’5’6 ’0.., undesired states 1, 3, 4, 7 must always go
to "0" on the next clock pulse.
UNIT-IV
Q8 (a) A combinational circuit is defined by the following function.
Fi (ABC) -m (4, 5, 7) (7+3)
F2 (ABC) = Jm (3, 5, 7)
Implement this circuit with a PLA having 3 inputs, 3 product terms and 2
outputs.
(b) State the various performance characteristics of ADC.
Q9 Write a short Note on
(i) Content Addressable Memory (10)
(ii) Dual-Slope ADC OR
Successive-Approximation ADC
 (Please write your Enrollment Number) Enrollment No.

Supplementary Examination
(CBCS)(SUBJECTIVE TYPE)(OffLine)
Course Name:<B.Tech. ECE-Al>, Semester:<ll>
(January 2024)
Subject Code: BEC 106 Subject: Signal & Systems
Time :3 Hours Maximum Marks :60
Note:Q. 1 is compulsory. Attempt one question each from the Units I, I1, I1l&IV.
Q1 (4*5-20)
(a) Verify the Parseval's theorem for energy signal x(t) =e3u(t)
(b) State the Dirichlet's conditions for Fourier series

(c) With the help of graphical example, state and prove sampling
theorem for low pass band-limited signals.
(d) State and prove initial value theorem and final value theorem of z
transforms.

UNIT-I
Q2 a) The input and impulse response to the system are (10)
given by: x(t) = ut + 1), h(t) = u(t-3). Determine
output of the system graphically.
b) For the signal shown in the Fig. 1, sketch the following:
i. x(2t)
ii. x(2t-3)

Fig. 1
O3 a) Check whether the following system is linear, Time (10)
invariant, Casual and Memory less or not: y(t) =
atx(t) + btx(t - 2)
b) A system produces an output of y (t) = e3u(t) for
an input of x(t) = eu(t). Determine the impulse
response and frequency response of the system.
UNIT-I
a Obtain the Fourier Transform of the following
(10)
functions:
i. Signum Function
ii. Rectangular pulse
b) Obtain the exponential Fourier series for the signal:
x() = -A,A, 0<tsn
TISts 2
Q5 a) Find the Fourier transform of the
following (10)
x(t) =e -a<t|
ii) x(t) = te 3u(t)
b) State and Prove time
Scaling property and frequency
differentiation property of Fourier Transform.
UNIT-II|
06 a) The frequency
(0.7 + 0.6 coswresponse
of a digital filter is,
- 0.9 cos2w)e H(ew) = (10)
M,
phase delay and Determine the
b) Compute the group delay.
Fourier transform and sketch
magnitude and phase function of causal three the sample
 sequenoe given by:
xn] =0snsz
Q7 else
a) Detemine the output sequence from the output (10)
sDectrum Y(e), where vlej)=le1+e"
b) Explain Min 3 1-ae-j
Phase system, Max phase system, all
System with example of each. pass
UNIT-IV
a) Find the inverse
tt ROC: |z>2
-transform of X(z) = 32-1
(1-z-)(1-22-1)
(10)
) If ROC: |z] <1
tt ROC:
b) Determine 1<|z| <2
the z-transform and
a^un]- b*u-n-1] where a>0ROCandfor xn]=
constants. b>0 are
a) Find the
-transform and ROC of Xz) for x(n) (10)
3) u(n) +2(-) u(n). Also find pole and zero
location.
b) Determine the unit step response of a discrete time
LM system, whose input
and
described by the differential output relation is
=x(n), where the equation,
initial condition y(n) +3
is yl-1) =1 y(n-1)
 END TERM Examinatioh
Semester:3
Course Name: MBA,
(November-December 2023)
Management System
Subject Code: MMS 245 Subject: Database Maximum Marks :60
Time :3 Hours
each from the Units I, I, II & V. (5,5,5,5)
NOte: Q. 1 is compulsoryv. Attempt one question
Q1 Answer the following question: -
ita concern in database design?
a) What is data redundancy, and why is
b) Enlist DDL and DML Commands
relational database.
C) Explain the concept of normalization in a
d) What is Big Data? Explain its 6 V's.
UNIT-I
its (10)
Q2 a) Describe the key components of a database management system and
role in managing data efficiently.
DBMS users.
b) Explain the different types and categories of (10)
library database system. The
Q3 Design an Entity-Relationship (ER) diagram for a
System needs to keep track of the following information:
Standard Book Number),
a) Books: Each book has a unique ISBN (International
(e.g., Fiction, Non-fiction,
a title, an author, a publication year, and a category
Science, Mystery, etc.).
a name,
b) Library Members: Library members have a unique member ID,
contact information, and a membership start date.
c) Borrowing Transactions: Each borrowing transaction has a member unique
return date. It also records which
transaction ID, a due date, and a
borrowed which book.
Design an ER diagram that represents these entities and their relationships.
Include the appropriate attributes and cardinality (e.g., one-to-many, many-to
many) for each relationship. Also specify the primary keys and foreign keys for
each entity to show how they are related in the database system.
UNIT-II
Q4 Explain the concept of data modeling database design. Explain the different
in (10)
types of data modelling techniques in DBMS.
Q5 What is 1 NE, 2 NF and 3 NF? Reduce the following table up till 3 NF: (10)
Full Name Address Movie Rented Salutation
Janet Jones Plot 4 First Street Pirates of Ms.
Caribbean, Clash
of Titans
Robert Phil 3rd Street 34 Forgetting Sarah, Mr.
Avenue Daddy's Little
Girl, Twilight
UNIT-|
Q6 What is SQL, and what is its primary purpose in the world of databases? What is (10)
a foreign key in aSQL table and explain its importance with help of any example.
Q7 Write SQL query for following consider table: (10)
EMP (empno, deptno, ename ,salary, Designation, joiningdate, DOB,city)
i) Write Commands for creating employee database,
ii) Display names of employees whose employee table.
ii) Display age of all the employees
experience is more than 10 years.
iv) Display average salary of all employees.
v) Display name of employee from highest to
lowest salary
UNIT-IV
Q8 Explain the need for NoSQL database. How is
explain the major characteristics of NOSQL. NOSQL different from RDBMS. Also
Q9 What is NOSQL? Explain the
major advantages and different categories of NOSOL (10)
disadvantages. Databases. State
(Please write your Enrollment Number) Enrollment No.

End-Term Examination
(CBCS)(SUBJECTIVE TYPE)(OffLine)
Course Name:B.Tech. (ECE), Semester:3rd
(November-December, 2023)

Subject Code: BEC 201 Subject: Analog Electronics

Maximum Marks :60
Time :3 Hours
Note:Q. 1iscompulsory. Attempt one question each from the Units I, II, Il & V.
2.5*8=20
Q1
when it is reverse
(a) Differentiate among types of capacitances present in aSi diode
level with
biased and forward biased. Comment on the change in capacitance
increase in reverse-bias potential for the Si diode.
(b Give principal of Zener diode and explain its usage as voltage regulator.
(C) Discuss the effect of temperature variation on operating point 'Q'.
V-l characteristiccurve.
(d How can we graphically find out transconductance 'gm' from
(e) What is pinch-off voltage? How it is affected by variation in gate to source voltage in
n-channel depletion type MOSFET?
Transformer Coupled
Give advantages of R-C coupled transistor amplifier over
transistor amplifier.
"base width
(e) Describe the phenomenon "channel length modulation" versus
modulation".
why JFET has
(h) Why the terminology field effect appropriate for JFET transistor and
high input impedance and effectively zero gate current?
UNIT-!
input (10)
Q2 Determine the output vo of the network given below in Fig. 1 if the
waveform v (given in Fig. 2) is applied to this network.
C= 1 uF
H
R 100 k 5
Vi
SV

Fig. 1
f= 1000 Hz

-20 -
Fig. 2

Q3 Identify the types of biasing techniques applied in circuits given below in fig. 3 (10)
and Fig.4. Compare both these techniques for the thermal stabilityprovided to
circuit in terms of Stability 'S' factor.

Page 1 of 2
 Flg. 3 Flg, 4
UNIT-I|
Q4 Analyze the circult glven In Fig. 5,using smallslgnal modelling (5SM) In amplifiers (10)
& find its voltage galn.

Re 3K

Rn tookn

Fig. 5
Q5 Write short notes on any two of the following : (10)
Cascaded Amplifiers
Darlington pair
T-Low frequency models
IV. Cascode Amplifiers
UNIT-I|I
Q6 What are different types of negative feedback topologies? Give comparative
analysis of them for the parameters (i) Nonlinear Distortion (ii) Noise (i) (10)
Bandwidth (iv) Input impedance (v) Output impedance. Give detailed block
diagrams for all these topologies.
Q7 Explain voltage and current operations of SCR and discuss its V-l
characteristics. (10)
UNIT-IV
Q8 Explain the working of n-channel JFET. What are the major
the collector characteristics of aBJT differences between (10)
transistor
JFET? Compare the units of each axis and the
and the drain characteristics of a
react to increasing levels of lo versus controlling variable. How does lc
of VGs?
changes in lo to increasing negative values
Q9 Sketch a p-channel enhancement type MOSFET and explain its working with
help of gate and drain characteristics the (10)
waveforms.

Page 2 of2
 (Please write your Enrollment Number) Enrollment No.

End-Term Examination- ONLINE MODE

(CBCS/Non-CBCS)(SUBJECTIVE TYPE)
<Programme Name B.Tech_><_3 SEM>
(DEC, 2021)
(SET A)
Subject Code:< BEC-201 Subject:< Analog Electronics >
Time: 1 Hour 15 minutes
Maximum Marks:30
Note: Q. 1 is compulsory. Attempt any one question from the rest.
Q1
(a) Describe the conditions established by forward- and
(5*3=15)
diode and how the resulting current is affected. Derive the reverse-bias conditions on a p-n junction
diode equation.
(b) i)For the Zener diode network of the fig below ,
ii) Repeat part (a) with RL =3 k. determine VL, VR,lz, and Pz .

Vy 10 v
Pzy = 30 mW

(c) What do you mean by

clipper circuit? Determine the output
below. waveform of the circuit given

V=sy
20 V

Q2
(a) Explain the
DC analysis and working of n-p-n
also evaluate VC[ type BJT in detail. (7.5+7.5= 15)
and Ic equations. Explain the voltage divider CE
(b) What are the hybrid
parameters? Convert a CE fixed bias circuit into
circuit. For the network below,
configuration
determine Zi, Zo, Av, Ai. h-parameter small signal
o8V

330 k«)
2.7 k4?

h 120

h,= 20 HAV

Q3
(a) Explain the
MOSFET and JFET.construction and
(b)
in What
details.is the benefit of
characteristics of JFET. Also define the (7.5+7.5= 15)
difference between
Multi-stage amplifier? Explain darlington pair emitter follower amplifier
 Enrollnment No.
Number)
(Please write your Enrollment
ONLINE MODE
End-Term Examination-
(CBCS/Non-CBCS)(SUBJECTIVE TYPE)
<Programme Name
B.Tech><_3_ SEM>
(DEC, 2021)
(SET B)
>
Subject:< Analog ElectronicsMaximum
Subject Code:< BEC-201 Marks : 30
Time:1 Hour 15 minutes
any one question from the rest.
Note: Q. 1 iscompulsory. Attempt
(5*3=15)
Q1 with suitable diagram.
explain the working of PN junction diode
(a) Derive the diode equation and range of RL and IL that will
of the fig below,determine the
(b) i) or the Zener diode network
result in VRL being maintained at 10 V.
rating of the diode.
ii) Determine the maximum wattage

circuit given
What do you mean by Clamper circuit? Determine the output waveform of the
(c)
below.

20 V

10V
-20 V

(7.5+7.5= 15)
Q2
follower amplifier
(a) What the benefit of Multi-stage amplifier? Explain darlington pair emitter
in details.
and find its
(b) Explain the construction and characteristics of depletion type MOSFET
characteristics equation. Also define the difference between MOSFET and JFET.

Q3 (7.5+7.5= 15)
(a) What are the hybrid parameters? Convert a CE fixed bias circuit into h-parameter small signal
circuit. For the network below, determine Zi,Zo, Av, Ai.
o8V

2.7 k2
330 k)

H
h= 120
1, h= 20 uAN

z,
(b) Explain the working of n-p-n type BJT in detail. Explain Emitter bias CE configuration andalso
evaluate VCE and Lc equations.
 (Please write your Enrollment Number) Enrollment No.

End-Term Examination- ONLINE MODE

(Non-CBCS_Reappear)(SUBJECTIVE TYPE)
<Programme Name B.Tech >_3_SEM>
(DEC, 2021)
(SET A)
Subject Code:< BEC-207 Subject:< AnalogElectronics I >
Time: 1 Hour 15 minutes Maximum Marks:30
Note: Q. 1 is compulsory. Attempt any one question from the rest.

Q1
(5*3=15)
(a) Describe the Ebers moll model for pnp transistor. Explain its significance.
(b) What is the need of Bias stabilization? What are the important factors which
stabilization?
affects the bias

(c) What are the hybrid parameters? Convert a CE fixed bias circuit into
circuit. For the network below, determine Zi, Zo, Av, Ai. h-parameter small signal

o8V

2.7 k2
330 kS2

Hi.
h= 120
h,, = 1.I75 kO
hay 20 PAN

Q2
(a) Explain the working of (7.5+7.5= 15))
DC analysis and also evaluaten-p-n type BJT indetail.
VcE and Iç equations.
Explain the voltage divider CE configuration
(b)Derive the expression for CE short
circuit current gain Aias a function of
frequency.

Q3
(a) Explain the
MOSFET and JFET.construction and characteristics of JFET. Also define the (7.5+7.5= 15)
difference between
(b) What is the benefit of
in details. Multi-stage amplifier? Explain darlington pair
emitter follower amplifier
 Enrollment No.
Enrollment Number)
(Please write your
ONLINE MODE
End-Term Examination-
(Non-CBCS_Reappear)(SUBJECTIVE TYPE)
<Programme Name B.Tech ><_3_ SEM>
(DEC, 2021)
(SET B)
Subject Code:< BEC-207 Subject:< Analog Electronics I >
Maximum Marks :30
Time:1 Hour 15 minutes
rest.
Note: Q. 1 is compulsory. Attempt any one question from the

Q1 (5*3=15)
(a) Explain the working of n-p-n type BJTin detail. Explain Emiter bias CE configuration and
also evaluate VcE and Ic equations.
(b) What is the concept of negative feedback and draw the schematic diagrams of four basic
negative feedback configurations.
(c) Draw the h-parameter equivalent circuit for a typical common emitter amplifier and
expression for Ai , Av, Ri and Ro. derive
Q2
(a) What is the benefit of Multi-stage (7.5+7.5= 15)
in details. amplifier? Explain darlington pair emitter follower amplifier
(b) Explain the construction and
characteristics equation. Also define thecharacteristics of depletion type
difference between MOSFET and find its
MOSFET and JFET.
Q3
(a) Explain the
working of SCR in details. Also write
(b) Discuss the
the difference (7.5+7.5= 15)
between TRIAC and
analysis of CD JFET DIAC.
amplifier.
 lla N

(Hs)s0EVE IVPE)om)

(Novenmb Dete, 034)

|ubjeet: baital Elestone

Q1
-29)

(0) hnw-nto is aNlvonpBewntay nlo, Juatity

() Simytiy: -AC (ARD) ARCO AAC

() Cont tho llowing espression in canonical POS fn

Y'-(4tR)(Ê )
(e) Dintate bameen ROM, IAL and PLA with helpof intenal einuiry,
(0 State the Bxcitation Table fn JK Nip-tlop and " Nip-lop
(2) Daw the logie diagram of 2-t0-4 line decoaler using NOR pites, Draw tls
tr1th table.

(h) Comprr between the CMOS and TT, logiofamilics

UNIT-I
Q2 Use K-Maps to minimize and express the function in SOP Ad POS (10)
fom. Implement both expressions using NAND gates only.
F= m(0, 1, 2,6, 7, 10, 12, 15) +)d (3, 8, 13, 14)
Q3 (a) The 74154 is a 4-to-16 decoder. The outputs are active low and
(5+5)
there are two gate control signals, G1 and G2. The decoder is
enabled when G1 and G2 are both equal to 0. Realize the lollowing
functions using 74154 and logic gates
Fi (W, X, Y, Z) = m(1,9, 12, 1S)
F: (w, X,Y, Z) - Xm (0, I,2, 3, 4, 5, 7, 8, 10, II, 12, 13)
(b) An equality detector gives the output Y = 1, if both the inputs A
and B are either lor 0
(i) Construct the truth table
(iü) Write the Boolean expressionof Y
(iii) Implement the circuit using NAND gates
only
UNIT-I|
Q4 (a) Construct a 3-bit Ring Counter using the JK flip
working with the waveforms w.r.t clock pulses. flops, Show the (5+5)
(b) With the help of
MOD-8 Down Ripple appropriate waveforins, explain the functioning of
Counter using negative edge
flops. triggered flip
Page 1 of 2
 Q5 (a) Detcrmine thec output state of a 4-bit SIPO shift register after 3 (4+6)
clock pulses if the serial in termínal is held HIGH and the initial
contents of the shift register is 1001.
(b) Desigrn a self-correcting synchronous counter with the following
binary scqucnce: 0, 1,3, 5, 7 and repcat using Tflip-flops.

UNIT-I|
Q6 (a) What is a flip flop? How is an SR flip flop realized employing (6+4)
(i) NOR gates
(ii) NAND gates

(6) Implemnent an 8:1 MUX using two 4:1 MUX(s) use block diagrams.
Q7
(a) AS-bit DAC produces Vo = 1.4Vfor adigital input of 00111. Find (8+2)
i) its % resolution,
(ü) step size (AV),
(iii) Vo for digital input of 11000 and
(iv) full scale analog voltage
(b)State the various performance characteristics of ADC.
UNIT-IV
Q8 A combinational circuít is defined by the
following function. (10)
F1 (ABC) =Sm (4, 5,7)
Fz (ABC) = m (3, 5, 7)
Implement this circuit with a PLA having 3 inputs, 3
2 outputs. product terms and
Write a short Note on
(i) Content Addressable (S+5)
(ii) Dual-Slope ADC ORMemory
Successive-Approximation ADC
(Please write your Enrollment Number) Enrollment No.

End-Term Examination- ONLINE MODE

(CBCS/Non-cBCs)(SUBJECTIVE TYPE)
<Programme Name_B.Tech. IT _3_ SEM>
(DEC, 2021)
(SET A)
Subject Code:< BIT 201 > Subject: < DBMS
Time: 1 Hour 15 minutes Maximum MarkS: 30
Note: Q.1is compulsory. Attempt any one question from the rest.
Q1 Forthe relation R{A,B,C,D,E) with FD set (B A, A’ C, BC ’ D, AC ’ BE)
(S3=15)
(a) Show that AC and BC are NOT candidate keys of R. What are candidate keys of R
(b) Which of the following is a good decomposition
i. R1(A,G D) and R2(B, A, E)
ii. R1(A,C, D, E) and R2(C, D, E)
(c) Should Rbe decomposed or should it be accepted as such?

Q2 Given the following log file:

(7.5+7.5= 15)
(start, T4);
(write, T4, A, 2,3);
(start, T1);
(write, T1, B, 5, 7);
(start, T2);
(write, T2, C, 1, 9);
(commit, T2);
(start, T3);
(write, T3, B, 7, 2);
(commit T3)

(a) What will be the final value of A, B andCif

i. UNDo/REDO algorithm is applied

ii. NO-UNDO/REDO is applied
(b) (0) A proposal is
received to use deferred update for the
this proposal? Justify your answer UNDO/REDO. Would you agree with
(ü) A proposal is received to use
update in place for the UNDO/REDO. Would you
this proposal? Justify your answer. agree with

Q3 The HR and Accounts

departments of an organization wish to update the
designation and salary of an employee from Asst. (7.5+7.5= 15)
Rs. 20,000 to Rs. 25,000 Engineer to Exec. Engineer and
relation, respectively. Data about employees is
available in a
Employee(Eno, Ename, Designation, Salary).
(a) Can there be lost
Can there be dirty updates? If yes then build a
reads? If not, schedule to show this.
then why not? If yes, then
build a schedule to show this
(b)Can there be
For the sd
scheduleunrepeatable
of lost reads? If not then why not? If yes,
updates then build a schedule to
serializability and show if it results inofrollback
(a) above, use the
or not. time stamping technique of Sictic
optimistic
 Enrollment No.
(Please write your Enrollment Number)
End-Term Examlnatlon
(CBCS)(SUBJECTIVE TYPE)(OffLine)
B.Tech ECE/ECE-AI llrd SEM
(November-December, 2023)
and synthesis
Subject: Network analysls Maximum Marks :60
Subject Code: BEC 205
Time :3 Hours Unlts I, I, 1&IV.
one questlon cach from the
Note:Q. 1is compulsory. Attempt
(2.5*8=20)
Q1
parameter.
(a) Derive hybrid parameters in terms of Z
(b) How do you find Thevinin's resistance?connected to a 230-V line. How long does it
A when
(c) A heater elenments draws 20
take to consume 60 kJ? relevant
and specify their importance with
(d) Differentiate analysis and synthesis
expression. function
Aseries RL circuit has R= 10KO,L= 10
Mh and C= 1 uf. Find the transfer
(e)
of the circuit.
for the network under maximum power
(f) Derive the expression of Maximum power
transfer condition.
RC circuit excited by a unit step
(g) Derive an expression for the decay current in an
voltage. What is the time constant of the circuit?
(h) Discuss Telegan's theorem.

UNIT-I
Q2 If two circuits Xand Yare to be connected in cascade. Give the two port (10)
parameters of the combination with diagram of cascade combination
Q3 Using nodal analysis find all branch currents (10)
for the following circuit

2 s2

UNIT-II
Q4 A
series RLC circuit withR= 2 ohm, L=1 Hand C= 0.5 Farad with the (10)
applied voltage V(t) =sin t. Find i (t) if the switch is closed at t= 0. Use
Laplace transform method.
Avoltage pulse of magnitude 8 Volts and duration 2 seconds extending (10)
from t=2 seconds to t=4 seconds is applied to a series RL circuit. Obtain
the expression for the current i(t).
UNIT-I||
Q6 Explain Hybrid and Transmission parameters with examples.
Q7 Explain the concept of interconnection of Two-Port networks. Show that (10)
H=H, + H, for two Two-Port networks, when (10)
these are connected in
series-parallel connection.
UNIT-IV
Q8 How is a physical network
admittance function. Discuss. realized by considering the driving point (10)
09 Find the first and second Cauer
forms of LC networks for the given
point impedance function driving (10)
Z(s) =(s +10s +9)/(s +4s)
 (Please write your Enrollment Number) Enrollment No..

End-Term Examination- ONLINEMODE

(CBCS/Non-CBCS)(SUBJECTIVE TYPE)
<Programme Name B.Tech.IT 3SEM>
(DEC, 2021)
(SET B)
Subject Code:< BIT 201> Subject:< DBMS
Time: 1 Hour 15 minutes
Maximum Marks : 30
Note: Q. 1 is compulsory. Attempt any one question from the rest.
Q1
(5*3=15)
(a) The following functional dependencies are given: AB >
A
CD,AF > D, DE ’E,C> G, F ’ E, G’
Verify the following and state if true or false.
i. {CF)' = {ACDEFG)
i. {AE }' ={ACDEFG}
What is a candidate key for the relation R(A, B, C, D,
(b) For the relation R(A, B, C, D) and FD E,F, G)
set: (A ’ B, A’ BC, C’ D), can we
i. A’C derive
ii. B’D
i. BCD
(c) Show that A> Bis a
Q2 relationship A:B::N:1
(a) Consider three
transactions T1, T2 and T3 with timestamp in the order T1 < (7.5+7.5= 15)
two resources Aand B. What is the
result of each of the following T2<T3. There are
schedules
i. r1(A); r2(A); r3(A);
i. r1(A); w3(A); T3
wi(B);w2(B); w3(B);
commit; r2(B); w2(A):
ii. r1(A); w2(A); w3(A);
r2(A):
(a) Draw a
dependency graph for the schedule r1(A); w2(A); r2(A);
serializable. Apply 2PL to the schedule and use the
w3(A); and determine if it is
deadlock. "total allocation" scheme to prevent
03
Consider the following schema of a car
renting agency
Vehicle(Vno, Vmake, Vtype, Vprice) (7.5+7.5= 15)
Driver(Dno. License Year, Experience, State)
Drives(Dno, Vno, Date, Start time, End Time)
There are two
proposals
would you choose and
to define
why? primary keys for Vehicle (a) Vno,
a.
Write SQL queries to do Vmake and (b) Vno. Wnc
the
i. Find all following
their make in s whose price is greater than 2
vehicle
order these by
ascending order lakhs and
 i. Find the erperience of those drivers who drove vehide urnber DL 2C
4745

b. For each of the queries above

i. Build the query tree and dearty idertify the heuristicsused
i. What is the order of execution of
operatios of eacth query

22
 End-Term Examination
(CBCS)(SUBJECTIVE TYPE)(OffLine)
Course Name:<B. Tech CSE/T/MAE/ECE/DMAM/ECE-A >, Semester:<3rd>
(November-December, 2023)

Subject Code: BIT 201 Subject: DBMS

Time :3 Hours
Maximum Marks :60
Note:Q. 1 is compulsory. Attempt one question each from the Units I, Il, IIl &IV.

Q1
(4*5=20)
a) Define database management system and what are it's various
applications? What are the different anomalies in designing a database?

b) What isatomicity of a transaction? Explain with example.

c) What are the various functionalities of a typical
system?
database management
d) What do you understand by conflict
of an example.
serializability? Explain with the help

UNIT-I
Q2 List and explain various data models used for database
design. (10)

Q3 What is Entityset and also define Relationship set. List and

symbols used to draw ER Diagram. explain the (10)

UNIT-I|
Q4
Write SQL Queries for following set of tables:
EMPLOYEE (EmpNo, Name, DoB, Address, Gender, (10)
Salary, DNumber)
DEPARTMENT (DNumber, Dname, ManagerEmpNo,
MnagerStartDate).
i) Display the Age of 'male
ii)Display all employees in employees.
'Marketing. Department named
i) Display the name of
employee. highest salary paid 'female
iv) Which employee is
v) Display the oldest manger in company?
name of department of the employee
'SMITH.
 (10)
and stepwise convert it
Q5 Create the E-R diagram for a university database
into arelational database using the mapping algorithm.

UNIT-II

Q6 Normalize following relation up to 3NF: (10)

Bank(acno, cust_name, ac_type, bal, int_rate, cust_city, branchld,
branch_nm, br_city)

Q7 What do you understand by functional dependencies? Given a relation (10)

R(A, B, C, D) and Functional Dependency set FD ={AB ’ CD, B’ C},
determine whether the given Ris in 2NF? If not convert it into 2 NF.

UNIT-IV
Q8 List and explain the various issues while transactions are
running (10)
concurrently in DBMS.
Q9 Explain Concurrency control with locking methods.
(10)
 (Please write your Enrollment Enrollment No.
Number)
End-Term Examination- ONLINE MODE
(CBCS)(SUBJECTIVE TYPE)
B.Tech. (ECE), 3 Semester
(December,2021)
| Subject Code: Subject: Signal &Systems
BEC-203 Maximum Marks :30
Time: 1 Hour 15 minutes
Note: Q. 1is compulsory.Attempt any one question from the rest.
Q.1 (5*3=15)
is an odd function. Explain with
(a) Show that the convolution of an odd and an even function
the help of examples.
(b) Consider a causal LTI system with xín] as input and vín] as output are related by the difference
equation.

Y[n] =Y[n-1] +X
[n]
Determine Y[n] if X[n] = 6(n-1)
(c) Determine the Fourier Series component of the periodic square wave signalgiven below:
a(e)

.2
(a) Discuss which property of Continuous Time Fourier Transform is (7.5+7.5= 15)
used in the Amplitude
Modulation of communication signals. Consider an exponentially damped sinusoidal
defined by wave
g(t)= e-t sin(w,t)u(t)
Find the Fourier Transform of g(t).
(b) Using z-transform find the
convolution of the following two signals:
x(n) = {1, -2, 1)

1,
Ka(n) = 0sns5
0, elsewhere

Q.3
(a)
Differentiate between DTFT and
Convergence (ROC) of Z-transform. Z-Transform. Discuss different properties (7.5+7.5= 15)
of
(b) Transfer Region of
functions of zero-order hold and ideal
below. Explain how these are interpolation filter
comparison for how will the used in reconstruction of signal from are given in figure
zero-order hold. higher order holds affect the its
Explain
sampled and reconstructed with the help of block output signal ifsamples.
used
Drawd
in place
signals. diagrams and graphical representations of
 Zoro oder
hold

Decdaration of the Paper Setter(s)

Ihave followed these instructions provided by theexamination
division for endterm exarnination,
December 2021 for paper setting with best of my knowledge
a. No direct questions such as
student can use the book/ onlinedefinitions, comparisons, díagrams etc has
resources directly to answer the questionbeen given where the
and
b. Ensured that each and
every question is verified and
c. Ensured that the paper
un- covers entire syllabus asintimated to the students, all the questions are
ambiguous, discussed with other teachers who are teaching the same
department and other departments related to the subject in the
followed university norms for setting up the coverage of the syllabus,
difficulty level etc. and
question paper.
Name of the Paper Setter: Dr.
Richa Yadav
Email ld: richayadav®igdtuw.ac.in
Mobile No:9711518602

The above paper Declaration

of the
is moderated and departmental Moderation Committee
Name of the HoD: Prof. Nidhi Goel followed above guidelines
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