Mosfet S A0002809502 1
Mosfet S A0002809502 1
Mosfet S A0002809502 1
Power Field Effect Transistor
N−Channel Enhancement−Mode Silicon Gate MTP8N50E
This high voltage MOSFET uses an advanced termination scheme
to provide enhanced voltage−blocking capability without degrading
performance over time. In addition, this advanced TMOS E−FET is TMOS POWER FET
designed to withstand high energy in the avalanche and commutation 8.0 AMPERES
modes. This new energy efficient design also offers a drain−to−source 500 VOLTS
RDS(on) = 0.8 OHM
diode with a fast recovery time. Designed for low voltage, high speed
switching applications in power supplies, converters, PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are critical
and offer additional safety margin against unexpected voltage
transients.
• Robust High Voltage Termination D
• Avalanche Energy Specified
• Source−to−Drain Diode Recovery Time Comparable
to a Discrete Fast Recovery Diode
G
• Diode is Characterized for Use in Bridge Circuits
• IDSS and VDS(on) Specified at Elevated Temperature S
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MTP8N50E
16 16
VGS = 10 V
TJ = 25°C 7V 14 VDS ≥ 10 V
8V
I D, DRAIN CURRENT (AMPS)
10
8.0 8.0
100°C
6.0
25°C
4.0 4.0
5V TJ = −55°C
2.0
0 0
0 2.0 4.0 6.0 8.0 10 12 14 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0 0.55
0 2.0 4.0 6.0 8.0 10 12 14 16 0 2.0 4.0 6.0 8.0 10 12 14 16
ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current Figure 4. On−Resistance versus Drain Current
and Temperature and Gate Voltage
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
2.5 100,000
VGS = 0 V
VGS = 10 V
ID = 8 A TJ = 125°C
2.0 10,000
IDSS, LEAKAGE (nA)
100°C
1.5 1,000
0.5 10
0 1.0
−50 −25 0 25 50 75 100 125 150 0 100 200 300 400 500
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
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MTP8N50E
4000 10,000
VGS = 0 V TJ = 25°C
VDS = 0 V VGS = 0 V TJ = 25°C
3000 Ciss
Ciss
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
1,000
2000
Ciss
Crss Coss
100
1000 Coss
Crss
Crss
0 10
−10 −5.0 0 5.0 10 15 20 25 10 100 1000
VGS VDS DRAIN−TO−SOURCE VOLTAGE (VOLTS)
12 400 1000
V DS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V GS, GATE−TO−SOURCE VOLTAGE (VOLTS)
QT TJ = 25°C
10 ID = 8 A
VDD = 250 V
300 VGS = 10 V
8.0
VGS
t, TIME (ns)
4.0 td(off)
TJ = 25°C 100 tr
2.0 ID = 8 A
tf
Q3 VDS td(on)
0 0 10
0 8.0 16 24 32 40 1.0 10 100
Qg, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (OHMS)
8.0 100
VGS = 20 V
TJ = 25°C
SINGLE PULSE
VGS = 0 V 10 s
I S , SOURCE CURRENT (AMPS)
TC = 25°C
I D, DRAIN CURRENT (AMPS)
6.0 10
100 s
4.0 1.0 1 ms
10 ms
dc
2.0 RDS(on) LIMIT
0.1
THERMAL LIMIT
PACKAGE LIMIT
0 0.01
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 0.1 1.0 10 100 1000
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Diode Forward Voltage versus Figure 12. Maximum Rated Forward Biased
Current Safe Operating Area
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MTP8N50E
600
300
200
100
0
25 50 75 100 125 150
TJ, STARTING JUNCTION TEMPERATURE (°C)
1.0
D = 0.5
TRANSIENT THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE
0.2
0.1
0.1
0.05
0.02
0.01
SINGLE PULSE
0.01
0.00001 0.0001 0.001 0.01 0.1 1.0 10
t, TIME (seconds)
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MTP8N50E
PACKAGE DIMENSIONS
CASE 221A−09
ISSUE AA
NOTES:
SEATING 1. DIMENSIONING AND TOLERANCING PER ANSI
−T− PLANE
Y14.5M, 1982.
B F C 2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
T S BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
4
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
Q A 0.570 0.620 14.48 15.75
STYLE 5:
1 2 3 PIN 1. GATE B 0.380 0.405 9.66 10.28
U 2. DRAIN C 0.160 0.190 4.07 4.82
H 3. SOURCE D 0.025 0.035 0.64 0.88
4. DRAIN F 0.142 0.147 3.61 3.73
K G 0.095 0.105 2.42 2.66
Z H 0.110 0.155 2.80 3.93
J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
L R N 0.190 0.210 4.83 5.33
V Q 0.100 0.120 2.54 3.04
J R 0.080 0.110 2.04 2.79
G S 0.045 0.055 1.15 1.39
T 0.235 0.255 5.97 6.47
D U 0.000 0.050 0.00 1.27
N V 0.045 −−− 1.15 −−−
Z −−− 0.080 −−− 2.04
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MTP8N50E
Notes
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MTP8N50E
E−FET and TMOS are trademarks of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,
including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.
SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or
death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold
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attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
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