Spartan-6 FPGA Packaging and Pinouts Product Specification - Xilinx

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Chapter 2: Pinout Tables Table 2-14: FG(G)676 Package—LX75, LX100, and LX150 (Cont’d) Bank Pin Description Pin Number BUFIO2 Region No Connect (NC) 5 IO_L3P_M5RESET_5 D23 RT 5 IO_L3N_M5A11_5 C24 RT 5 IO_L4P_M5CKE_5 F22 RT 5 IO_L4N_M5A12_5 D22 RT 5 IO_L5P_M5A8_5 H20 RT 5 IO_L5N_M5A9_5 H21 RT 5 IO_L6P_M5A10_5 H22 RT 5 IO_L6N_M5A4_5 G22 RT 5 IO_L7P_M5WE_5 E23 RT 5 IO_L7N_M5BA2_5 E24 RT 5 IO_L8P_M5A7_5 G23 RT 5 IO_L8N_M5A2_5 G24 RT 5 IO_L9P_M5BA0_5 H18 RT 5 IO_L9N_M5BA1_5 G19 RT 5 IO_L10P_M5A0_5 B24 RT 5 IO_L10N_M5A1_5 A25 RT 5 IO_L11P_M5CLK_5 C25 RT 5 IO_L11N_M5CLKN_5 C26 RT 5 IO_L12P_M5A3_5 B25 RT 5 IO_L12N_M5ODT_5 B26 RT 5 IO_L13P_M5A5_5 K20 RT 5 IO_L13N_M5A6_5 K21 RT 5 IO_L14P_M5RASN_5 K22 RT 5 IO_L14N_M5CASN_5 J22 RT 5 IO_L15P_M5UDM_5 J23 RT 5 IO_L15N_M5LDM_5 J24 RT 5 IO_L16P_M5DQ4_5 E25 RT 5 IO_L16N_M5DQ5_5 E26 RT 5 IO_L17P_M5DQ6_5 D24 RT 5 IO_L17N_M5DQ7_5 D26 RT 5 IO_L18P_M5LDQS_5 F24 RT 5 IO_L18N_M5LDQSN_5 F26 RT 5 IO_L19P_M5DQ2_5 H24 RT 176 www.xilinx.com Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011
Table 2-14: FG(G)676 Package—LX75, LX100, and LX150 (Cont’d) 5 IO_L19N_M5DQ3_5 H26 RT 5 IO_L20P_M5DQ0_5 G25 RT 5 IO_L20N_M5DQ1_5 G26 RT 5 IO_L21P_M5DQ8_5 K24 RT 5 IO_L21N_M5DQ9_5 K26 RT 5 IO_L22P_M5DQ10_5 J25 RT 5 IO_L22N_M5DQ11_5 J26 RT 5 IO_L23P_M5UDQS_5 M24 RT 5 IO_L23N_M5UDQSN_5 M26 RT 5 IO_L24P_M5DQ12_5 L25 RT 5 IO_L24N_M5DQ13_5 L26 RT 5 IO_L25P_M5DQ14_5 N25 RT 5 IO_L25N_M5DQ15_5 N26 RT 5 IO_L26P_5 L20 RT 5 IO_L26N_VREF_5 L21 RT 5 IO_L27P_5 H19 RT 5 IO_L27N_5 J20 RT 1 IO_L28P_1 L19 RT 1 IO_L28N_VREF_1 K19 RT 1 IO_L29P_A23_M1A13_1 L23 RT 1 IO_L29N_A22_M1A14_1 L24 RT 1 IO_L30P_A21_M1RESET_1 P20 RT 1 IO_L30N_A20_M1A11_1 N21 RT 1 IO_L31P_A19_M1CKE_1 M23 RT 1 IO_L31N_A18_M1A12_1 N24 RT 1 IO_L32P_A17_M1A8_1 L17 RT 1 IO_L32N_A16_M1A9_1 K18 RT 1 IO_L33P_A15_M1A10_1 P24 RT 1 IO_L33N_A14_M1A4_1 P26 RT 1 IO_L34P_A13_M1WE_1 M19 RT 1 IO_L34N_A12_M1BA2_1 L18 RT 1 IO_L35P_A11_M1A7_1 R25 RT 1 IO_L35N_A10_M1A2_1 R26 RT FG(G)676 Package—LX75, LX100, and LX150 Bank Pin Description Pin Number BUFIO2 Region No Connect (NC) Spartan-6 FPGA Packaging www.xilinx.com 177 UG385 (v2.2) August 24, 2011
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Spartan-6 FPGA Packaging and Pinout
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Date Version Revision 10/12/10 1.3
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Table of Contents Revision History
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CSG324 Chip-Scale BGA Package Speci
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About This Guide Organization of Th
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Packaging Overview Summary Introduc
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Device/Package Combinations and Max
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Device/Package Combinations and Max
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Pin Definitions Table 1-6: Spartan-
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Table 1-6: Spartan-6 FPGA Pin Defin
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Table 1-6: Spartan-6 FPGA Pin Defin
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X-Ref Target - Figure 1-2 X-Ref Tar
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GTP Transceiver Locations Clock Inp
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Pinout Tables Summary Chapter 2 Thi
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Table 2-2: TQG144 Package—LX4 and
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Table 2-2: TQG144 Package—LX4 and
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CPG196 Package—LX4, LX9, and LX16
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Table 2-3: CPG196 Package—LX4, LX
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Table 2-4: CSG225 Package—LX4 (Co
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Table 2-5: CSG225 Package—LX9 and
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Table 2-6: FT(G)256 Package—LX9,
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CSG324 Package—LX9, LX16, LX25, a
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Table 2-7: CSG324 Package—LX9, LX
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Table 2-8: CSG324 Package—LX25T a
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FG(G)484 Package—LX25, LX45, LX75
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Table 2-9: FG(G)484 Package—LX25,
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FG(G)484 Package—LX25T, LX45T, LX
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CS(G)484 Package—LX45, LX75, LX10
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Table 2-11: CS(G)484 Package—LX45
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Table 2-11: CS(G)484 Package—LX45
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Table 2-16: FG(G)900 Package—LX15
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Pinout and I/O Bank Diagrams Summar
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X-Ref Target - Figure 3-2 P1 P2 P3
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X-Ref Target - Figure 3-13 X-Ref Ta
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X-Ref Target - Figure 3-24 A B C D
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Mechanical Drawings Summary Chapter
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X-Ref Target - Figure 4-2 CPG196 Ch
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X-Ref Target - Figure 4-4 FT(G)256
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FG(G)484 Fine-Pitch BGA Package Spe
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X-Ref Target - Figure 4-7 FG(G)676
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Thermal Specifications Summary Intr
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Table 5-1: Thermal Resistance Data
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X-Ref Target - Figure 5-2 Die Attac
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Soldering Guidelines moisture / ref
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X-Ref Target - Figure 5-5 Temperatu
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Package Marking Chapter 6 The Spart
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Density Migration Introduction Comp
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No Connects Table 7-2 and Table 7-3
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X-Ref Target - Figure 7-1 Encryptio
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PlanAhead Software Tool PlanAhead S
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