Spartan-6 FPGA Packaging and Pinouts Product Specification - Xilinx

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Chapter 4: Mechanical Drawings X-Ref Target - Figure 4-8 FG(G)900 Chip-Scale BGA Package Specifications (1.00 mm Pitch) Figure 4-8: FG(G)900 Chip-Scale BGA Package ug385_c4_09_111809 340 www.xilinx.com Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011
Thermal Specifications Summary Introduction Chapter 5 This chapter provides thermal data associated with Spartan-6 FPGA packages. The following topics are discussed: Introduction Cavity-Up Plastic BGA Packages Support for Compact Thermal Models (CTM) Soldering Guidelines References Spartan-6 devices are offered in a wide variety of packages. The suite of packages is used to address the various power requirements of the Spartan-6 devices. All Spartan-6 devices are implemented in the 45 nm process technology All Spartan-6 devices feature versatile SelectIO resources that support a variety of I/O standards. They also include DSPs and other traditional features and blocks (such as block RAM) contained in earlier Spartan and Virtex® products. In line with Moore's law, the transistor count in this family of devices has been increased substantially. Though several innovative features at the silicon level have been deployed to minimize power dissipation, including leakage at the 45 nm node, these products have more densely packed transistors and embedded blocks with the capability to run faster than before. Thus, a fully configured Spartan-6 FPGA design that exploits the internal logic speed and incorporates several embedded circuits and systems can present power consumption challenges that must be managed. Unlike features in an ASIC or a microprocessor, the combination of FPGA features used in a user application are not known to the component supplier. Therefore, it remains a challenge for Xilinx to predict the power requirements of a given FPGA when it leaves the factory. Accurate estimates are obtained when the board design takes shape. For this purpose, Xilinx offers and supports a suite of integrated device power analysis tools to help users quickly and accurately estimate their design power requirements. Spartan-6 devices are supported similarly to previous FPGA products. The uncertainty of design power requirements makes it difficult to apply canned thermal solutions to fit all users. Therefore, Xilinx devices do not come with preset thermal solutions. The user’s operating conditions dictate the appropriate solution. Spartan-6 FPGA Packaging www.xilinx.com 341 UG385 (v2.2) August 24, 2011
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Spartan-6 FPGA Packaging and Pinout
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Date Version Revision 10/12/10 1.3
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Table of Contents Revision History
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CSG324 Chip-Scale BGA Package Speci
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About This Guide Organization of Th
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Packaging Overview Summary Introduc
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Device/Package Combinations and Max
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Device/Package Combinations and Max
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Pin Definitions Table 1-6: Spartan-
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Table 1-6: Spartan-6 FPGA Pin Defin
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Table 1-6: Spartan-6 FPGA Pin Defin
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X-Ref Target - Figure 1-2 X-Ref Tar
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GTP Transceiver Locations Clock Inp
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Pinout Tables Summary Chapter 2 Thi
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Table 2-2: TQG144 Package—LX4 and
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Table 2-2: TQG144 Package—LX4 and
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CPG196 Package—LX4, LX9, and LX16
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Table 2-3: CPG196 Package—LX4, LX
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Table 2-4: CSG225 Package—LX4 (Co
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Table 2-5: CSG225 Package—LX9 and
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Table 2-6: FT(G)256 Package—LX9,
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CSG324 Package—LX9, LX16, LX25, a
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Table 2-7: CSG324 Package—LX9, LX
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Table 2-8: CSG324 Package—LX25T a
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FG(G)484 Package—LX25, LX45, LX75
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Table 2-9: FG(G)484 Package—LX25,
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FG(G)484 Package—LX25T, LX45T, LX
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CS(G)484 Package—LX45, LX75, LX10
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Table 2-11: CS(G)484 Package—LX45
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CS(G)484 Package—LX45T, LX75T, LX
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FG(G)676 Package—LX45 FG(G)676 Pa
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Table 2-13: FG(G)676 Package—LX45
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FG(G)676 Package—LX75T, LX100T, a
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Pinout and I/O Bank Diagrams Summar
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X-Ref Target - Figure 3-2 P1 P2 P3
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X-Ref Target - Figure 3-13 X-Ref Ta
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X-Ref Target - Figure 3-24 A B C D
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X-Ref Target - Figure 3-26 A B C D
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Page 331 and 332: Mechanical Drawings Summary Chapter
Page 333 and 334: X-Ref Target - Figure 4-2 CPG196 Ch
Page 335 and 336: X-Ref Target - Figure 4-4 FT(G)256
Page 337 and 338: FG(G)484 Fine-Pitch BGA Package Spe
Page 339: X-Ref Target - Figure 4-7 FG(G)676
Page 343 and 344: Table 5-1: Thermal Resistance Data
Page 345 and 346: X-Ref Target - Figure 5-2 Die Attac
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Page 349 and 350: X-Ref Target - Figure 5-5 Temperatu
Page 351 and 352: Package Marking Chapter 6 The Spart
Page 353 and 354: Density Migration Introduction Comp
Page 355 and 356: No Connects Table 7-2 and Table 7-3
Page 357 and 358: X-Ref Target - Figure 7-1 Encryptio
Page 359 and 360: PlanAhead Software Tool PlanAhead S
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Spartan-6 FPGA Packaging and Pinouts Product Specification - Xilinx

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