Spartan-6 FPGA Packaging and Pinouts Product Specification - Xilinx

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Chapter 2: Pinout Tables Table 2-4: CSG225 Package—LX4 (Cont’d) Bank Pin Description Pin Number BUFIO2 Region No Connect (NC) 3 IO_L38N_3 M1 LB 3 IO_L39P_3 L2 LB 3 IO_L39N_3 L1 LB 3 IO_L40P_3 K3 LB 3 IO_L40N_3 K1 LB 3 IO_L41P_GCLK27_3 J2 LB 3 IO_L41N_GCLK26_3 J1 LB 3 IO_L42P_GCLK25_TRDY2_3 H3 LB 3 IO_L42N_GCLK24_3 H1 LB 3 IO_L43P_GCLK23_3 K4 LT 3 IO_L43N_GCLK22_IRDY2_3 J3 LT 3 IO_L44P_GCLK21_3 G2 LT 3 IO_L44N_GCLK20_3 G1 LT 3 IO_L45P_3 K5 LT 3 IO_L45N_3 J4 LT 3 IO_L46P_3 F3 LT 3 IO_L46N_3 F1 LT 3 IO_L52P_3 E2 LT 3 IO_L52N_3 E1 LT 3 IO_L53P_3 D4 LT 3 IO_L53N_3 E3 LT 3 IO_L54P_3 D3 LT 3 IO_L54N_3 D1 LT 3 IO_L83P_3 C2 LT 3 IO_L83N_VREF_3 C1 LT NA GND A1 NA NA GND A15 NA NA GND B10 NA NA GND B6 NA NA GND C13 NA NA GND C3 NA NA GND E11 NA NA GND F14 NA 44 www.xilinx.com Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011
Table 2-4: CSG225 Package—LX4 (Cont’d) NA GND F2 NA NA GND F6 NA NA GND G7 NA NA GND G9 NA NA GND H8 NA NA GND J7 NA NA GND J9 NA NA GND K14 NA NA GND K2 NA NA GND K6 NA NA GND L11 NA NA GND N13 NA NA GND N3 NA NA GND P10 NA NA GND P6 NA NA GND R1 NA NA GND R15 NA NA VCCINT F9 NA NA VCCINT G6 NA NA VCCINT G8 NA NA VCCINT H7 NA NA VCCINT H9 NA NA VCCINT J10 NA NA VCCINT J8 NA NA VCCINT K7 NA NA VCCAUX B1 NA NA VCCAUX E12 NA NA VCCAUX F7 NA NA VCCAUX G10 NA NA VCCAUX J6 NA NA VCCAUX K9 NA NA VCCAUX L4 NA NA VCCAUX M12 NA CSG225 Package—LX4 Bank Pin Description Pin Number BUFIO2 Region No Connect (NC) Spartan-6 FPGA Packaging www.xilinx.com 45 UG385 (v2.2) August 24, 2011
Page 1 and 2: Spartan-6 FPGA Packaging and Pinout
Page 3 and 4: Date Version Revision 10/12/10 1.3
Page 5 and 6: Table of Contents Revision History
Page 7 and 8: CSG324 Chip-Scale BGA Package Speci
Page 9 and 10: About This Guide Organization of Th
Page 11 and 12: Packaging Overview Summary Introduc
Page 13 and 14: Device/Package Combinations and Max
Page 15 and 16: Device/Package Combinations and Max
Page 17 and 18: Pin Definitions Table 1-6: Spartan-
Page 19 and 20: Table 1-6: Spartan-6 FPGA Pin Defin
Page 21 and 22: Table 1-6: Spartan-6 FPGA Pin Defin
Page 23 and 24: X-Ref Target - Figure 1-2 X-Ref Tar
Page 25 and 26: GTP Transceiver Locations Clock Inp
Page 27 and 28: Pinout Tables Summary Chapter 2 Thi
Page 29 and 30: Table 2-2: TQG144 Package—LX4 and
Page 31 and 32: Table 2-2: TQG144 Package—LX4 and
Page 33 and 34: CPG196 Package—LX4, LX9, and LX16
Page 35 and 36: Table 2-3: CPG196 Package—LX4, LX
Page 41 and 42: Table 2-4: CSG225 Package—LX4 (Co
Page 43: Table 2-4: CSG225 Package—LX4 (Co
Page 47 and 48: Table 2-4: CSG225 Package—LX4 (Co
Page 49 and 50: Table 2-5: CSG225 Package—LX9 and
Page 57 and 58: Table 2-6: FT(G)256 Package—LX9,
Page 65 and 66: CSG324 Package—LX9, LX16, LX25, a
Page 67 and 68: Table 2-7: CSG324 Package—LX9, LX
Page 77 and 78: Table 2-8: CSG324 Package—LX25T a
Page 87 and 88: FG(G)484 Package—LX25, LX45, LX75
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Table 2-9: FG(G)484 Package—LX25,
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FG(G)484 Package—LX25T, LX45T, LX
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CS(G)484 Package—LX45, LX75, LX10
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Table 2-11: CS(G)484 Package—LX45
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CS(G)484 Package—LX45T, LX75T, LX
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FG(G)676 Package—LX45 FG(G)676 Pa
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Table 2-13: FG(G)676 Package—LX45
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FG(G)676 Package—LX75T, LX100T, a
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Pinout and I/O Bank Diagrams Summar
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X-Ref Target - Figure 3-2 P1 P2 P3
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X-Ref Target - Figure 3-5 X-Ref Tar
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X-Ref Target - Figure 3-9 X-Ref Tar
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X-Ref Target - Figure 3-13 X-Ref Ta
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X-Ref Target - Figure 3-24 A B C D
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Mechanical Drawings Summary Chapter
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X-Ref Target - Figure 4-2 CPG196 Ch
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X-Ref Target - Figure 4-4 FT(G)256
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FG(G)484 Fine-Pitch BGA Package Spe
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X-Ref Target - Figure 4-7 FG(G)676
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Thermal Specifications Summary Intr
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Table 5-1: Thermal Resistance Data
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X-Ref Target - Figure 5-2 Die Attac
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Soldering Guidelines moisture / ref
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X-Ref Target - Figure 5-5 Temperatu
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Package Marking Chapter 6 The Spart
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Density Migration Introduction Comp
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No Connects Table 7-2 and Table 7-3
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X-Ref Target - Figure 7-1 Encryptio
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PlanAhead Software Tool PlanAhead S
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