Spartan-6 FPGA Packaging and Pinouts Product Specification - Xilinx

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Chapter 3: Pinout and I/O Bank Diagrams X-Ref Target - Figure 3-3 X-Ref Target - Figure 3-4 CPG196 Package—LX4, LX9, and LX16 User I/O Pins IO_LXXY_# A B C D E F G H J K L M N P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 I A H K M B O C D E F G H J K Z L g W A M P Y 1 N C D N b U B 0 P Multi-Function Pins VREF C CCLK P_GCLK B CSI N_GCLK b CSO D0 - D15 N DIN A0 - A25 A DOUT_BUSY a FCS / FWE / FOE H HSWAPEN / HDC / LDC Y INIT U RDWR_B_VREF 1 0 M1, M0 W AWAKE Dedicated Pins P PROGRAM_B_2 K TCK I TDI O TDO M TMS D DONE_2 Z SUSPEND g CMPCS_B_2 Other Pins UG385_c3_03_111909 Figure 3-3: CPG196 Package—LX4, LX9, and LX16 Pinout Diagram A B C D E F G H J K L M N P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 0 0 0 0 0 0 0 0 0 0 A 3 0 0 0 0 0 0 0 0 0 0 0 B 3 0 0 1 1 C 3 3 3 3 0 0 1 1 D 3 3 1 1 E 3 3 3 3 1 1 1 1 F 3 3 1 1 G 3 3 1 1 1 1 H 3 3 3 3 1 1 1 1 J 3 3 1 1 K 3 3 2 2 1 1 L 3 3 2 2 1 1 M 2 2 2 2 2 2 2 2 2 2 2 2 N 2 2 2 2 2 2 2 2 2 2 2 2 P 1 2 3 4 5 6 7 8 9 10 11 12 13 14 UG385_c3_04_110209 Figure 3-4: CPG196 Package—LX4, LX9, and LX16 I/O Bank Diagram 274 www.xilinx.com Spartan-6 FPGA Packaging UG385 (v2.2) August 24, 2011 n GND VCCAUX VCCINT VCCO NC
X-Ref Target - Figure 3-5 X-Ref Target - Figure 3-6 User I/O Pins IO_LXXY_# CSG225 Package—LX4 A B C D E F G H J K L M N P R 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 H n n n O n n n n I M n n n n n n n n n n n n n n n n n n g Z n n n 1 C Y N W A P b U B 0 D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Multi-Function Pins VREF C CCLK P_GCLK B CSI N_GCLK b CSO D0 - D15 N DIN A0 - A25 A DOUT_BUSY a FCS / FWE / FOE H HSWAPEN / HDC / LDC Y INIT U RDWR_B_VREF 1 0 M1, M0 W AWAKE Figure 3-5: CSG225 Package—LX4 Pinout Diagram A B C D E F G H J K L M N P R Figure 3-6: CSG225 Package—LX4 I/O Bank Diagram UG385_c3_05_111909 CSG225 Package—LX4 Spartan-6 FPGA Packaging www.xilinx.com 275 UG385 (v2.2) August 24, 2011 K A B C D E F G H J K L M N P R Dedicated Pins P PROGRAM_B_2 K TCK I TDI O TDO M TMS D DONE_2 Z SUSPEND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 g CMPCS_B_2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0 0 0 A 0 0 0 0 0 0 0 1 1 B 3 3 0 0 0 0 0 0 0 0 1 1 C 3 3 3 0 0 0 0 1 1 D 3 3 3 0 0 1 1 E 3 3 0 1 1 F 3 3 1 1 G 3 3 1 1 H 3 3 3 3 1 1 1 1 J 3 3 3 3 2 1 1 1 1 1 K 3 3 3 2 2 2 2 1 1 1 L 3 3 3 2 2 2 2 1 1 M 3 3 2 2 2 2 2 2 2 2 1 1 N 3 3 2 2 2 2 2 2 1 1 P 2 2 2 2 2 2 2 2 2 2 2 R UG385_c3_06_110209 Other Pins n GND VCCAUX VCCINT VCCO NC
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Spartan-6 FPGA Packaging and Pinout
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Date Version Revision 10/12/10 1.3
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Table of Contents Revision History
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CSG324 Chip-Scale BGA Package Speci
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About This Guide Organization of Th
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Packaging Overview Summary Introduc
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Device/Package Combinations and Max
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Device/Package Combinations and Max
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Pin Definitions Table 1-6: Spartan-
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Table 1-6: Spartan-6 FPGA Pin Defin
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Table 1-6: Spartan-6 FPGA Pin Defin
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X-Ref Target - Figure 1-2 X-Ref Tar
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GTP Transceiver Locations Clock Inp
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Pinout Tables Summary Chapter 2 Thi
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Table 2-2: TQG144 Package—LX4 and
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Table 2-2: TQG144 Package—LX4 and
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CPG196 Package—LX4, LX9, and LX16
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Table 2-3: CPG196 Package—LX4, LX
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Table 2-4: CSG225 Package—LX4 (Co
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Table 2-5: CSG225 Package—LX9 and
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Table 2-6: FT(G)256 Package—LX9,
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CSG324 Package—LX9, LX16, LX25, a
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Table 2-7: CSG324 Package—LX9, LX
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Table 2-8: CSG324 Package—LX25T a
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FG(G)484 Package—LX25, LX45, LX75
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Table 2-9: FG(G)484 Package—LX25,
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FG(G)484 Package—LX25T, LX45T, LX
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CS(G)484 Package—LX45, LX75, LX10
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Table 2-11: CS(G)484 Package—LX45
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CS(G)484 Package—LX45T, LX75T, LX
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FG(G)676 Package—LX45 FG(G)676 Pa
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Table 2-13: FG(G)676 Package—LX45
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FG(G)676 Package—LX75T, LX100T, a
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Page 223 and 224: Table 2-16: FG(G)900 Package—LX15
Page 271 and 272: Pinout and I/O Bank Diagrams Summar
Page 273: X-Ref Target - Figure 3-2 P1 P2 P3
Page 277 and 278: X-Ref Target - Figure 3-9 X-Ref Tar
Page 279 and 280: X-Ref Target - Figure 3-13 X-Ref Ta
Page 285 and 286: X-Ref Target - Figure 3-24 A B C D
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X-Ref Target - Figure 3-64 A B C D
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Mechanical Drawings Summary Chapter
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X-Ref Target - Figure 4-2 CPG196 Ch
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X-Ref Target - Figure 4-4 FT(G)256
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FG(G)484 Fine-Pitch BGA Package Spe
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X-Ref Target - Figure 4-7 FG(G)676
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Thermal Specifications Summary Intr
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Table 5-1: Thermal Resistance Data
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X-Ref Target - Figure 5-2 Die Attac
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Soldering Guidelines moisture / ref
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X-Ref Target - Figure 5-5 Temperatu
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Package Marking Chapter 6 The Spart
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Density Migration Introduction Comp
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No Connects Table 7-2 and Table 7-3
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X-Ref Target - Figure 7-1 Encryptio
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PlanAhead Software Tool PlanAhead S
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Spartan-6 FPGA Packaging and Pinouts Product Specification - Xilinx

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