EXPERIMENT NO.

Instrumentation and Programmable Gain Amplifiers

Date: PS No.:____2_____ Batch No.___5_____

_____14/2/17____________
ID No. Name: ______Praneeth Kumar Maddula________
________2014AAPS284H__
______

Aim: To study the performance of Instrumentation and Programmable gain amplifiers.

Equipment & Components: Analog Electronics Trainer kit, DSO & Function Generator (Analog Discovery kit),
Digital Multi Meter, 741 ICs, JFETs (2N3819), Resistors, Connecting wires.

Theory:

Introduction:

1. Instrumentation Amplifier (IA)

An Instrumentation Amplifier is a closed-loop gain amplifier that has a differential input and single-ended output. Most
9
commonly, the impedances of the two input terminals are balanced and have high values, typically 10 or greater.
The input bias currents are also low, typically 1 nA to 50 nA. The output impedance is very low, nominally only a few
milliohms, at low frequencies.

Instrumentation amplifiers are made up of two parts: buffered amplifiers

A1 , A 2 and a basic differential amplifier

A 3 . The buffered amplifiers A 1 and A 2 not only provide gain, but prevent the sensor resistance from affecting

the resistors in the difference amplifier circuit, and vice-versa.

Figure 5.1 shows a classic three op-amp variable gain instrumentation amplifier. The full differential input voltage appears

across
R1 .Since the amplified input voltage (at the outputs of the buffers) appears differentially across the three

R 2 , R1 R2 , the differential gain may be varied by just changing R1 .

resistors, and Another advantage of this
connection is that once the subtractor circuit has been set up with its ratio-matched resistors, no further resistor matching
is required when changing gains.

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 Figure 5.1 Instrumentation Amplifier

RF '
V 1V 2
'

The output voltage

V o is given by V o= ),
RI

R1 '
V 1V 2
'

Also,
V 1V 2 = ),
R 1+2 R2

2 R2 RF
Therefore, V o= 1+ (
V 1V 2 .
R1 RI

V /R
Since the voltage across
R1 equals V = ( V 1V 2 , the current through 1 ). Buffers, therefore, operate
R1=

with gain and amplify the input signal. If a common-mode voltage is applied to the amplifier inputs, the voltages on each

side of
R1 will be equal and no current will flow through this resistor. Since no current flows through
R1 (and,

R2 , the buffer amplifiers operate as unity gain followers. Therefore, common-mode signals
therefore, through both

2 R2
are passed through the input buffers at unity gain, but differential voltages will be amplified by the factor 1+ R1

. The front end gain can be increased by varying R without increasing the common mode gain and error. The
1

differential signal will be increased by gain, but the common mode error will not, so the ratio will increase. Thus, CMRR
will theoretically increase in direct proportion to gain.

Programmable Gain Amplifier (PGA)

In many applications, amplifiers having facility of gain variation under remote program control of a microprocessor are
needed. A typical inverting type of PGA using FET switches and an op-amp is shown in Figure 5.2. The FET switch is ON
when the gate voltage is high or logic 1. The gain magnitude for different states of the FET switches are shown in the
accompanying table (S = 1, closed and S = 0, open).

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 (a) (b)

Figure 5.2 (a) Inverting PGA and (b) gain for different switch conditions

(a) (b)
Figure 5.3 (a) A non-inverting PGA and (b) gain for different switch conditions.

S1 S2 , S3
A PGA of a non- inverting type is shown in Figure 5.3. The switches , shown in this PGA can be
electronic switches. The amplifier gain can be controlled by closing and opening the switches. For different conditions of
the switches, the table gives the amplifier gain (S = 1, closed and S = 0, open).

Observations:

Use A 741 Op-amp with dc power supply voltages of 15V.

Run1:Programmable gain amplifier (PGA)

1.1 Assemble the PGA circuit of Figure 5.2(a). Use 2N3819 JFET as a switch which operates at 0 V (ON) and 15 V

(OFF). Apply dc input voltage

VI = 0.1 V, Note down the output voltage,
Vo (volts) and verify the gain at the
switch positions given in the Table 5.1 for inverting PGA.

Table 5.1:

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 (Gain)
Output VO
Switch(es) AV = (Gain)
voltage VI

Vo
S1 S2 S3 S4 Practical Theoretical
(volts)
0 0 0 0 10.34 100.3 100
1 0 0 0 5.17 51.7 50
0 1 0 0 1.08 10.8 10
0 0 1 0 0.200 2 2
0 0 0 1 0.100 1 1

1.2 Design a non-inverting type PGA

Design a non-inverting PGA as shown in Figure 5.3a to have programmable gains of 1, 3, 5 and 9. Assume a resistance
R1 (instead of
RF ) between the output and the inverting input. Then determine R1 in terms of RF for the

R1=
desired gain for the positions of the switches as given in the tabular column 5.2 of Figure 5.3a. Show that 2

RF .

Design:

R1
1+4 ( ) RF
=9

Hence
R1=2 RF .

We have taken
RF to be 20 kilo-ohm.

Assemble the PGA circuit (Ref. Fig 5.3a). Use 2N3819 JFET as a switch which operates at 0 V (ON) and 15 V

(OFF). Choose the appropriate standard component values.

V i = 1 V. Note down the output voltage, V o (volts) and Verify the gain at different
1.3 Apply dc input voltage
switch positions given in Table 5.2 for non-inverting PGA (Figure 5.3a).

Table 5.2:

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 (Gain)
Output VO
Switch(es) voltage AV = (Gain)
VI
Run2: Instrumentation
Vo Amplifier (IA)
S1 S2 S3 Practical Theoretical
(volts) 2.1 Design:
0 0 0 1 1 1
Using Equation,
1 0 0 3 3 3 2 R2 RF
0 1 0 5 5 5 V o= 1+ (
R1 RI
0 0 1 9 9 9
V 1V 2 , determine the value of

R1 of an instrumentation amplifier as shown in Figure 5.1 for the gain of 630. Let R2 = 470 , RF = 270 k,
RI = 9.1 K .

Design:

R1=47

2.2 Make common mode gain of the differential amplifier zero:

First assemble circuit as shown in Figure 5.4(a). Here, we want to make the common mode gain of the amplifier A 3 to be
zero. Short both the input terminals (nodes 6 and 7) and apply +5 V dc to this shorted node. Measure the output voltage, (
V o .If this is not zero, split the resistor of value 270 K connected to the non-inverting input of A into the series
3

combination of fixed resistor of 220 K and potentiometer of 100 K as shown in Fig 5.4(b). Vary the pot to make the

output (
V o of A 3 to zero.

Figure 5.4(a): Circuit for making common mode gain of A3 to be zero (b) Circuit for RF equivalent

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2.3 Determine common mode gain (Ac ) of the IA for dc inputs

Remove the short between the nodes 6 and 7. Assemble the circuit as shown in Fig 5.1. Short the nodes 1 and 2 and apply
V 1=V 2=5 V to this shorted node. Measure the output voltage V o . This voltage divided by 5 gives
+5 V dc ( i. e

the common mode voltage gain

A c of the Instrumentation Amplifier. Also observe the voltages at nodes 6 and 7 with

respect to ground.

' ' V 1 +V 2
V o= __332 mV____, V 2= __4.25 V_____, V 1 =___4.24 V____, V cm =
2 = ___4.245

Vo
V_____,
Ac = =_____0.078 V______.
V cm

2.4 Determine differential gain (Ad ) and CMRR of the IA for dc inputs

V 1= +5 mV dc at node 1 and V 2= 5mV dc at node 2.

Remove the short between the nodes 1 and 2. Apply

Measure the output voltage

V o . This voltage divided by 10 gives the difference mode voltage gain A d of the

Instrumentation Amplifier. Also observe the voltages at nodes 6 and 7 with respect to ground.

Use 10 k potentiometer for obtaining the +5 mV and 5mV dc as shown in Fig 5.5. Vary the 10 k pot and adjust
resistance value to obtain +/- 5 mV as shown in Figure 5.5. Calculate CMRR for dc signal.

Figure 5.5: Circuit for applying +/- 5mV dc

' '
V o= __14.14 V____, V 2= ____-3.88 V___, V 1 =__2.5 V_____, V id = V 1V 2 =

Vo Ad
__10 mV______,
Ad = =_____1414______, CMRR = | = ___42.5_____ (dB)
V id Ac

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2.5 Determine common mode gain (Ac ) of the IA for ac inputs

V 2=V 1= 50 mVp-p ac input signal frequency of 1 kHz to this shorted node.

Now short the nodes 1 and 2 and feed
V o . Calculate the common mode voltage gain A c of the Instrumentation Amplifier. Also
Measure the output voltage
observe the voltages at nodes 6 and 7 with respect to ground.

V 1 +V 2 Vo
V o= ______, V '2= _______, V '1 =_______, V cm = = ________,
Ac =
2 V cm

=___________.

2.6 Determine differential gain (Ad ) and CMRR of the IA for ac inputs

V 1= 50 mVp-p ac input signal frequency of 1 KHz at node 1 and

Remove the short between the node 1 and 2. Feed
V 2= 25 mVp-p at node 2. Use the circuit shown in Fig. 5.6 to obtain 50 mVp-p and 25 mVp-p signals. Measure
Vo Ad .
and hence calculate Also observe the voltages at nodes 6 and 7 with respect to ground. Calculate the
CMRR for ac signal.

Figure 5.6: Circuit for applying 50 mVp-p and 25 mVp-p ac

V o= ______, V '2= _______, V '1 =_______, V id = V 1V 2 = ________, Ad =

Vo Ad
=___________, CMRR = | = ________ (dB)
V id Ac

Conclusions:

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The operation of an op-amp as an instrumentation amplifier and as a PGA were studied.

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