Analysis of SRAM Bitcells Using Ultralow-Voltage Schmitt-Trigger Based Design
Analysis of SRAM Bitcells Using Ultralow-Voltage Schmitt-Trigger Based Design
Analysis of SRAM Bitcells Using Ultralow-Voltage Schmitt-Trigger Based Design
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Analysis of SRAM bitcells using Ultralow-Voltage Schmitt-Trigger based Design
10T SRAM
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International Journal of Engineering and Technical Research (IJETR)
ISSN: 2321-0869, Volume-2, Issue-4, April 2014
Thus, read bitline does not require precharge and keeper Fig.3 shows the schematics of the ST-1 bitcell. The ST-1
transistor. Also, the read-bitline toggling is avoided if the bitcell utilizes differential sensing with ten transistors, one
accessed data are unchanged. A differential 10T bitcell with word-line (WL), and two bitline (BL/BR). Transistors
two separate ports for read-disturb- free operation [19]. The PL-NL1-NL2-NFL forms one ST inverter while
read-disturb-free differential 10T bitcell is suitable for PR-NR1-NR2-NFR forms another ST inverter. Feedback
bit-interleaved architecture [20]. However, series-connected transistors NFL/NFR raise the switching threshold of the
write access transistors degrade the write-ability of the bitcell inverter during the 01 input transition giving the ST action.
and needs write-assist circuits such as word-line boosting for
a successful write operation.
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Analysis of SRAM bitcells using Ultralow-Voltage Schmitt-Trigger based Design
Fig. 5 Output Schematic waveforms for 4T, 6T, 8T, 10T &
ST-1, ST-2 SRAM bitcell
No. of
Transist Ivdd Avg_ Avg_ Tplh Tphl
or delay power
SRAM
Bitcell
V. CONCLUSION
The proposed ST based SRAM bitcell gives more stability
in read operation with reduced power supply voltage and
correspondingly the read failure probability also decreases as
compare to conventional 6T SRAM bitcell. Lowering the
supply voltage is an effective way to achieve ultra-low-power
operation. Here the evaluated ST based SRAM bitcells
suitable for ultra-low voltage applications. The proposed ST
based bitcell can be effective for process-tolerant,
low-voltage SRAM operation in future nano scaled
technologies. Simulation results show that the ST based
bitcell can retain the data at low supply voltage.
264 www.erpublication.org
International Journal of Engineering and Technical Research (IJETR)
ISSN: 2321-0869, Volume-2, Issue-4, April 2014
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