PD-91896F

IRF1404
HEXFET® Power MOSFET
l Advanced Process Technology
l Ultra Low On-Resistance D
l Dynamic dv/dt Rating VDSS = 40V
l 175°C Operating Temperature
l Fast Switching RDS(on) = 0.004Ω
l Fully Avalanche Rated G
l Automotive Qualified (Q101)
ID = 202A†
S
Description
Seventh Generation HEXFET® Power MOSFETs from
International Rectifier utilize advanced processing
techniques to achieve extremely low on-resistance per
silicon area. This benefit, combined with the fast
switching speed and ruggedized device design that
HEXFET power MOSFETs are well known for, provides
the designer with an extremely efficient and reliable
device for use in a wide variety of applications including
automotive.

The TO-220 package is universally preferred for all

automotive-commercial-industrial applications at power TO-220AB
dissipation levels to approximately 50 watts. The low
thermal resistance and low package cost of the TO-220
contribute to its wide acceptance throughout the industry.
Absolute Maximum Ratings
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 202†
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 143† A
IDM Pulsed Drain Current  808
PD @TC = 25°C Power Dissipation 333 W
Linear Derating Factor 2.2 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche Energy‚ 620 mJ
IAR Avalanche Current See Fig.12a, 12b, 15, 16 A
EAR Repetitive Avalanche Energy‡ mJ
dv/dt Peak Diode Recovery dv/dt ƒ 1.5 V/ns
TJ Operating Junction and -55 to + 175
TSTG Storage Temperature Range -55 to + 175 °C
Soldering Temperature, for 10 seconds 300 (1.6mm from case )
Mounting Torque, 6-32 or M3 screw 10 lbf•in (1.1N•m)

Thermal Resistance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 0.45
RθCS Case-to-Sink, Flat, Greased Surface 0.50 ––– °C/W
RθJA Junction-to-Ambient ––– 62

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Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 40 ––– ––– V VGS = 0V, ID = 250µA
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient ––– 0.039 ––– V/°C Reference to 25°C, ID = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– 0.0035 0.004 Ω VGS = 10V, ID = 121A „
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = 10V, ID = 250µA
gfs Forward Transconductance 76 ––– ––– S VDS = 25V, ID = 121A
––– ––– 20 VDS = 40V, VGS = 0V
IDSS Drain-to-Source Leakage Current µA
––– ––– 250 VDS = 32V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 200 VGS = 20V
IGSS nA
Gate-to-Source Reverse Leakage ––– ––– -200 VGS = -20V
Qg Total Gate Charge ––– 131 196 ID = 121A
Qgs Gate-to-Source Charge ––– 36 ––– nC VDS = 32V
Qgd Gate-to-Drain ("Miller") Charge ––– 37 56 VGS = 10V„
td(on) Turn-On Delay Time ––– 17 ––– VDD = 20V
tr Rise Time ––– 190 ––– ID = 121A
ns
td(off) Turn-Off Delay Time ––– 46 ––– RG = 2.5Ω
tf Fall Time ––– 33 ––– RD = 0.2Ω „
Between lead, D
LD Internal Drain Inductance ––– 4.5 –––
6mm (0.25in.)
nH
from package G

LS Internal Source Inductance ––– 7.5 –––

and center of die contact S

Ciss Input Capacitance ––– 5669 ––– VGS = 0V

Coss Output Capacitance ––– 1659 ––– pF VDS = 25V
Crss Reverse Transfer Capacitance ––– 223 ––– ƒ = 1.0MHz, See Fig. 5
Coss Output Capacitance ––– 6205 ––– VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
Coss Output Capacitance ––– 1467 ––– VGS = 0V, VDS = 32V, ƒ = 1.0MHz
Coss eff. Effective Output Capacitance … ––– 2249 ––– VGS = 0V, VDS = 0V to 32V

Source-Drain Ratings and Characteristics

Parameter Min. Typ. Max. Units Conditions
IS Continuous Source Current MOSFET symbol D

––– ––– 202†

(Body Diode) showing the
A
ISM Pulsed Source Current integral reverse G

––– ––– 808

(Body Diode)  p-n junction diode. S

VSD Diode Forward Voltage ––– ––– 1.5 V TJ = 25°C, IS = 121A, VGS = 0V „
trr Reverse Recovery Time ––– 78 117 ns TJ = 25°C, IF = 121A
Qrr Reverse RecoveryCharge ––– 163 245 nC di/dt = 100A/µs „
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
 Repetitive rating; pulse width limited by „ Pulse width ≤ 400µs; duty cycle ≤ 2%.
max. junction temperature. (See fig. 11)
… Coss eff. is a fixed capacitance that gives the same charging time
‚ Starting TJ = 25°C, L = 85µH as Coss while VDS is rising from 0 to 80% VDSS
RG = 25Ω, IAS = 121A. (See Figure 12)
† Calculated continuous current based on maximum allowable
ƒ ISD ≤ 121A, di/dt ≤ 130A/µs, VDD ≤ V(BR)DSS, junction temperature. Package limitation current is 75A.
TJ ≤ 175°C

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1000 VGS
1000 VGS
TOP 15V TOP 15V
10V 10V
I D , Drain-to-Source Current (A)

I D , Drain-to-Source Current (A)

8.0V 8.0V
7.0V 7.0V
6.0V 6.0V
5.5V 5.5V
5.0V 5.0V
BOTTOM 4.5V BOTTOM4.5V
100 100

4.5V

10 10
4.5V

20µs PULSE WIDTH 20µs PULSE WIDTH

TJ = 25 °C TJ = 175 °C
1 1
0.1 1 10 100 0.1 1 10 100
VDS , Drain-to-Source Voltage (V) VDS , Drain-to-Source Voltage (V)

Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics

1000 2.5
ID = 202A
RDS(on) , Drain-to-Source On Resistance
I D , Drain-to-Source Current (A)

TJ = 25 ° C
2.0
TJ = 175 ° C
(Normalized)

1.5

100

1.0

0.5

V DS= 25V
20µs PULSE WIDTH VGS = 10V
10 0.0
4 5 6 7 8 9 10 11 12 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS , Gate-to-Source Voltage (V) TJ , Junction Temperature ( ° C)

Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance

Vs. Temperature
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10000 20
VGS = 0V, f = 1 MHZ ID = 121A
V DS= 32V
Ciss = Cgs + Cgd, Cds SHORTED

VGS , Gate-to-Source Voltage (V)

V DS= 20V
8000 Crss = Cgd
16
Coss = Cds + Cgd
C, Capacitance(pF)

6000 Ciss
12

4000
Coss
8

2000

4
Crss
0
FOR TEST CIRCUIT
1 10 100 SEE FIGURE 13
0
0 50 100 150 200
VDS, Drain-to-Source Voltage (V) QG , Total Gate Charge (nC)

Fig 5. Typical Capacitance Vs. Fig 6. Typical Gate Charge Vs.

Drain-to-Source Voltage Gate-to-Source Voltage

1000 10000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
ISD , Reverse Drain Current (A)

TJ = 175 ° C
100 1000
ID , Drain Current (A)

10us

10 100 100us

TJ = 25 ° C
1ms

1 10 10ms

TC = 25 °C
TJ = 175 °C
V GS = 0 V Single Pulse
0.1 1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 1 10 100
VSD ,Source-to-Drain Voltage (V) VDS , Drain-to-Source Voltage (V)

Fig 7. Typical Source-Drain Diode Fig 8. Maximum Safe Operating Area

Forward Voltage
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220 RD
VDS
200 LIMITED BY PACKAGE
VGS
180 D.U.T.
RG
ID , Drain Current (A)

160 +
-V DD
140
10V
120
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
100

80
Fig 10a. Switching Time Test Circuit
60

40 VDS
90%
20

0
25 50 75 100 125 150 175
TC , Case Temperature ( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs. td(on) tr t d(off) tf
Case Temperature
Fig 10b. Switching Time Waveforms

1
Thermal Response (Z thJC )

D = 0.50

0.1 0.20

0.10
0.05
0.02 SINGLE PULSE
0.01 (THERMAL RESPONSE) PDM
0.01
t1
t2

Notes:
1. Duty factor D = t 1 / t 2
2. Peak TJ = P DM x Z thJC + TC
0.001
0.00001 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)

Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case

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IRF1404

1500

EAS , Single Pulse Avalanche Energy (mJ)

15V
ID
TOP 49A
101A
L DRIVER 1200 BOTTOM 121A
VDS

RG D.U.T +
V 900
- DD
IAS A
20V
tp 0.01Ω
600
Fig 12a. Unclamped Inductive Test Circuit
V(BR)DSS
tp 300

0
25 50 75 100 125 150 175
Starting TJ , Junction Temperature ( ° C)
I AS

Fig 12b. Unclamped Inductive Waveforms Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
QG

10 V
QGS QGD 4.0
-VGS(th) Gate threshold Voltage (V)

VG

3.0
Charge ID = -250µA

Fig 13a. Basic Gate Charge Waveform

Current Regulator
Same Type as D.U.T.
2.0
50KΩ

12V .2µF
.3µF

+
V
D.U.T. - DS
1.0
VGS -75 -50 -25 0 25 50 75 100 125 150

3mA T J , Temperature ( °C )

IG ID
Current Sampling Resistors
Fig 14. Threshold Voltage Vs. Temperature
Fig 13b. Gate Charge Test Circuit
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1000

Duty Cycle = Single Pulse

0.01 Allowed avalanche Current vs

Avalanche Current (A)

100 avalanche pulsewidth, tav

assuming ∆ Tj = 25°C due to
0.05 avalanche losses

0.10

10

1
1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)

Fig 15. Typical Avalanche Current Vs.Pulsewidth

400 Notes on Repetitive Avalanche Curves , Figures 15, 16:

TOP Single Pulse (For further info, see AN-1005 at www.irf.com)
350 BOTTOM 10% Duty Cycle 1. Avalanche failures assumption:
ID = 121A Purely a thermal phenomenon and failure occurs at a
EAR , Avalanche Energy (mJ)

300 temperature far in excess of Tjmax. This is validated for

every part type.
250
2. Safe operation in Avalanche is allowed as long asTjmax
is not exceeded.
3. Equation below based on circuit and waveforms shown
200
in Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
150
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
100 voltage increase during avalanche).
6. Iav = Allowable avalanche current.
50 7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
0 tav = Average time in avalanche.
25 50 75 100 125 150 175 D = Duty cycle in avalanche = t av ·f
Starting T J , Junction Temperature (°C) ZthJC(D, tav) = Transient thermal resistance, see figure 11)

PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC

Iav = 2DT/ [1.3·BV·Zth]
Fig 16. Maximum Avalanche Energy EAS (AR) = PD (ave)·tav
Vs. Temperature

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IRF1404

Peak Diode Recovery dv/dt Test Circuit

+ Circuit Layout Considerations

D.U.T
• Low Stray Inductance
• Ground Plane
ƒ
• Low Leakage Inductance
Current Transformer
-

+
‚
„
- +
-


RG • dv/dt controlled by RG +
• Driver same type as D.U.T. VDD
-
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test

Driver Gate Drive

P.W.
Period D=
P.W. Period

VGS=10V *

D.U.T. ISD Waveform

Reverse
Recovery Body Diode Forward
Current Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
VDD

Re-Applied
Voltage Body Diode Forward Drop
Inductor Curent

Ripple ≤ 5% ISD

* VGS = 5V for Logic Level Devices

Fig 17. For N-channel HEXFET® Power MOSFETs

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TO-220AB Package Outline
Dimensions are shown in millimeters
10.54 (.415) 3.78 (.149) -B-
2.87 (.113) 10.29 (.405) 3.54 (.139) 4.69 (.185)
2.62 (.103) 4.20 (.165)
-A- 1.32 (.052)
1.22 (.048)
6.47 (.255)
6.10 (.240)
4
15.24 (.600)
14.84 (.584)
1.15 (.045) LEAD ASSIGNMENTS
MIN 1 - GATE
1 2 3 2 - DRAIN
3 - SOURCE
4 - DRAIN
14.09 (.555)
13.47 (.530) 4.06 (.160)
3.55 (.140)

0.93 (.037) 0.55 (.022)

3X 3X
0.69 (.027) 0.46 (.018)
1.40 (.055)
3X
1.15 (.045) 0.36 (.014) M B A M
2.92 (.115)
2.64 (.104)
2.54 (.100)
2X
NOTES:
1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.

TO-220AB Part Marking Information

EXAMPLE: THIS IS AN IRF1010
LOT CODE 1789
ASS EMB LED ON WW 19, 1997 INTERNAT IONAL PART NUMB ER
IN THE ASS EMB LY LINE "C" RECTIFIER
LOGO
Note: "P" in assembly line DAT E CODE
position indicates "Lead-Free" YEAR 7 = 1997
ASS EMBLY
LOT CODE WEEK 19
LINE C

For GB Production
EXAMPLE: THIS IS AN IRF1010
LOT CODE 1789
AS SEMBLED ON WW 19, 1997 INTERNATIONAL PART NUMBER
IN T HE AS SEMBLY LINE "C" RECTIFIER
LOGO

DATE CODE
LOT CODE

TO-220AB package is not recommended for Surface Mount Application.

Data and specifications subject to change without notice.

This product has been designed and qualified for the automotive [Q101] market.
Qualification Standards can be found on IR’s Web site.

IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.01/01
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/