Outline - The MOS Capacitor (Cont'd) : - Small-Signal Capacitance
Outline - The MOS Capacitor (Cont'd) : - Small-Signal Capacitance
OUTLINE
The MOS Capacitor
(contd)
Small-signal
capacitance
(C-V characteristics)
S and W vs. VG
(p-type Si)
2 F
S:
0
accumulation
2
qN A si
2Cox (VG VFB )
1
s
1
2
qN A si
2Cox
accumulation
2 Si (2F )
qN A
2
2 SiS
Si
2Cox (VG VFB )
1
W
1
qN A
Cox
qN A si
(for VFB VG VT )
VG
WT
W:
VG
(for VFB VG VT )
ox
FB
depletion
accumulation
VFB
accumulation
inversion
VT
depletion
VFB
inversion
VG
accumulation
depletion
inversion
VT
VG
Qdep qN AW
accumulation
VG
depletion
VFB
0
inversion
VT
VG
VT
Qinv
slope = -Cox
VFB
MOS Capacitance
Measurement
VG is scanned slowly
MOS Capacitor
Capacitive current d
to vac is measured
C-V Meter
iac
vac
GATE
Semiconductor
dvac
iac C
dt
dQGATE
dQs
C
dVG
dVG
depletion
inversion
VG
VFB
VT
dQs
C
dVG
Qinv
slope = -Cox
Cox
VT
depletion
inversion
Capacitance in
Accumulation
(p-type Si)
As the gate voltage is varied, incremental
charge is added (or subtracted) to (or from) the
gate and substrate.
The incremental charges are separated by the
M
O
S
gate oxide.
Q
Q
-Q
dQacc
C
Cox
dVG
Cox
EE130/230M Spring 2013
Flat-Band Capacitance
(p-type Si)
At the flat-band condition, variations in VG give
rise to the addition/subtraction of incremental
charge in the substrate, at a depth LD
LD is the extrinsic Debye Length, a characteristic screening
distance, or the distance where the electric field emanating
from a perturbing charge falls off by a factor of 1/e
Si kT
LD
q2 N A
Cox
CDebye
1
1
LD
CFB Cox Si
Lecture 17, Slide 7
Capacitance in Depletion
(p-type Si)
As the gate voltage is varied, the depletion
width varies.
Incremental charge is effectively added/subtracted
at a depth W in the substrate.
M
W
-Q
Cox
EE130/230M Spring 2013
dQdep
dVG
2(VG VFB )
1
2
qN A Si
Cox
Cdep
1
1
1
1 W
Capacitance in Inversion
(p-type Si)
CASE 1: Inversion-layer charge can be
supplied/removed quickly enough to
respond to changes in gate voltage.
layer
charge = 2NAo/ni , where
o = minority-carrier lifetime at
surface
dQ
Cox
EE130/230M Spring 2013
inv
dVG
Cox
Capacitance in Inversion
(p-type Si)
CASE 2: Inversion-layer charge cannot be
supplied/removed quickly enough to
respond to changes in gate voltage.
depth W
in
the
substrate.
C C
C
MT
O
S
ox
WT
Q
Cox
EE130/230M Spring 2013
Cdep
dep
1 WT
Cox Si
1
2(2 F )
1
Cox
qN A Si C min
Supply of Substrate
Charge
(p-type
Si)
Accumulation:
Depletion:
Inversion:
Case 1
Case 2
Cmax=Cox
CFB
Cmin
accumulation
VFB
depletion
VT
inversion
VG
Quasi-Static C-V
Measurement
(p-type
Si)
C
Cmax=Cox
CFB
Cmin
accumulation
VFB
depletion
VT
inversion
VG
Deep Depletion
(p-type Si)
If VG is scanned quickly, Qinv cannot respond to the
change in VG. Then the increase in substrate charge
density Qs must come from an increase in depletion
charge density Qdep
depletion depth W increases as VG increases
C decreases as VG increases
C
Cox
Cmin
VFB
EE130/230M Spring 2013
VT
VG
Cmax=Cox
CFB
VT
Cmin
depletion
VFB
inversion
VG
Examples: C-V
Characteristics
C
QS
Cox
HF-Capacitor
VFB
VT
VG
Example: Effect of
Doping
How would the normalized C-V characteristic
below change if the substrate doping NA were
increased?
VFB
VT
Cmin
C/Cox
1
VFB
EE130/230M Spring 2013
VT
C/Cox
1
VFB
EE130/230M Spring 2013
VT